AMIS−30523
http://onsemi.com
24
Because of the relatively high recirculation currents in the
coil during current decay, the coil voltage V
COIL
shows a
transient behavior. As this transient is not always desired in
application software, two operating modes can be selected
by means of the bit <SLAT> (see “SLA−transparency” in
Table 15 SPI Control Parameter Overview). The SLA pin
shows in “transparent mode” full visibility of the voltage
transient behavior. This allows a sanity−check of the
speed−setting versus motor operation and characteristics
and supply voltage levels. If the bit “SLAT” is cleared, then
only the voltage samples at the end of each coil current zero
crossing are visible on the SLA−pin. Because the transient
behavior of the coil voltage is not visible anymore, this mode
generates smoother Back e.m.f. input for post−processing,
e.g. by software.
In order to bring the sampled Back e.m.f. to a descent
output level (0 to 5 V), the sampled coil voltage V
COIL
is
divided by 2 or by 4. This divider is set through an SPI bit
<SLAG> (see Table 15 SPI Control Parameter Overview).
The following drawing illustrates the operation of the
SLA−pin and the transparency−bit. “PWMsh” and “I
coil
= 0”
are internal signals that define together with SLAT the
sampling and hold moments of the coil voltage.
More information can be found in application note
AND8399/D.
PWMsh
SLAT
SLA−Pin
last
retained
retain last sample
previous output is
buf
Ssh Sh
Ch
Csh
SLAT
NOT (Icoil=0)
Icoil=0
PWMsh
SLA−Pin
div2
div4
t
t
Figure 21. Timing Diagram of SLA−Pin
SLAT = 1 => SLA−pin is “transparent” during
V
BEMF
sampling @ Coil Current Zero
Crossing. SLA−pin is updated “real−time”.
SLAT = 0 => SLA−pin is not “transparent”
during V
BEMF
sampling @ Coil Current Zero
Crossing. SLA−pin is updated when leaving
current−less state.
V
COIL
V
COIL
V
BEMF
sample
is
kept at SLA pin
Icoil=0
Warning, Error Detection and Diagnostics Feedback
Thermal Warning and Shutdown
When junction temperature rises above T
TW
, the thermal
warning bit <TW> is set (Table 17 SPI Status registers
Address SR0). If junction temperature increases above
thermal shutdown level, then the circuit goes in “Thermal
Shutdown” mode (<TSD>) and all driver transistors are
disabled (high impedance) (see Table 17 SPI Status registers
Address SR2). The conditions to reset flag <TSD> is to be
at a temperature lower than T
TW
and to clear the <TSD> flag
reading out Status Register 2.
Over−Current Detection
The over−current detection circuit monitors the load
current in each activated output stage. If the load current
exceeds the over−current detection threshold, then the
over−current flag is set and the drivers are switched off to
reduce the power dissipation and to protect the integrated
circuit. Each driver transistor has an individual detection bit
in (see Table 17 SPI Status registers Address SR1 and SR2:
<OVCXij> and <OVCYij>). Error condition is latched
and the microcontroller needs to clear the status bits (by
reading Status Register 1 or 2) to reactivate the drivers.
