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AMIS30523C5231G

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P35
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Table 14. SPI CONTROL REGISTERS (All SPI control registers have Read/Write Access and default to ”0” after power−on or
hard reset.)
Address
Content
Structure
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
WR (00h) Data WDEN WDT[3:0] − − −
CR0 (01h) Data SM[2:0] CUR[4:0]
CR1 (02h) Data DIRCTRL NXTP − − PWMF PWMJ EMC[1:0]
CR2 (03h) Data MOTEN SLP SLAG SLAT − − − −
Where:
R/W Read and Write access
Reset: Status after power−On or hard reset
Table 15. SPI CONTROL PARAMETER OVERVIEW
Symbol Description Status Value
DIRCTRL
Controls the direction of rotation
(in combination with logic level on input DIR)
<DIR> = 0
<DIRCTRL> = 0 CW motion
<DIRCTRL> = 1 CCW motion
<DIR> = 1
<DIRCTRL> = 0 CCW motion
<DIRCTRL> = 1 CW motion
NXTP
Selects if NXT triggers on rising or falling
edge
<NXTP> = 0 Trigger on rising edge
<NXTP> = 1 Trigger on falling edge
EMC[1:0]
Turn On – Turn−off Slopes of motor driver
(Note 18)
00 Very Fast
01 Fast
10 Slow
11 Very Slow
SLAT Speed load angle transparency bit
<SLAT> = 0 SLA is transparent
<SLAT> = 1 SLA is NOT transparent
SLAG Speed load angle gain setting
<SLAG> = 0 Gain = 0.5
<SLAG> = 1 Gain = 0.25
PWMF
Enables doubling of the PWM frequency
(Note 18)
<PWMF> = 0 Default Frequency
<PWMF> = 1 Double Frequency
PWMJ Enables jittery PWM
<PWMJ> = 0 Jitter disabled
<PWMJ> = 1 Jitter enabled
SM[2:0] Stepmode
000 1/32 Micro − Step
001 1/16 Micro − Step
010 1/8 Micro − Step
011 1/4 Micro − Step
100 Compensated Half Step
101 Uncompensated Half Step
110 Full Step
111 n.a.
SLP Enables sleep mode
<SLP> = 0 Active mode
<SLP> = 1 Sleep mode
MOTEN Activates the motor driver outputs
<MOTEN> = 0 Drivers disabled
<MOTEN> = 1 Drivers enabled
18.The typical values can be found in Table 5: DC Parameters Motor Driver and in Table 6: AC parameters Motor Driver
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CUR[4:0] Selects IMCmax peak. This is the peak or amplitude of the regulated current waveform in the motor coils.
Table 16. SPI CONTROL PARAMETER OVERVIEW CUR[4:0]
Current Range
(Note 20)
Index CUR[4:0]
Current (mA)
(Note 19)
Current Range
(Note 20)
Index CUR[4:0]
Current (mA)
(Note 19)
0
0 00000 33
2
16 10000 365
1 00001 64 17 10001 400
2 00010 95 18 10010 440
3 00011 104 19 10011 485
4 00100 115 20 10100 530
5 00101 126 21 10101 585
6 00110 138 22 10110 630
7 00111 153
3
23 10111 750
8 01000 166 24 11000 825
1
9 01001 190 25 11001 895
10 01010 205 26 11010 975
11 01011 230 27 11011 1065
12 01100 250 28 11100 1155
13 01101 275 29 11101 1245
14 01110 300 30 11110 1365
15 01111 325
31 11111
1480
19.Typical current amplitude at T
J
= 125°C
20.Reducing the current over different current ranges might trigger overcurrent detection. See application note AND8372/D for solutions.
SPI Status Register Description
All 4 SPI status registers have Read Access and are default to “0” after power−on or hard reset.
Table 17. SPI STATUS REGISTERS
Address
Content
Structure
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Access R R R R R R R R
Reset 0 0 0 0 0 0 0 0
SR0 (04h) Data is not latched PAR TW CPfail WD OPENX OPENY − −
SR1 (05h) Data is latched PAR OVCXPT OVCXPB OVCXNT OVCXNB − − −
SR2 (06h) Data is latched PAR OVCYPT OVCYPB OVCYYNT OVCYNB TSD − −
SR3 (07h) Data is not latched PAR MSP[6:0]
Where:
R Read only mode access
Reset Status after power−on or hard reset
PAR Parity check
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Table 18. SPI STATUS FLAGS OVERVIEW
Mnemonic Flag
Length
(bit)
Related
SPI Register
Comment
Reset
State
CPFail Charge pump failure 1 Status Register 0 ‘0’ = no failure
‘1’ = failure: indicates that the charge pump
does not reach the required voltage level.
‘0’
MSP[6:0] Micro−step position 7 Status Register 3 Translator micro step position ‘0000000’
OPENX OPEN Coil X 1 Status Register 0 ‘1’ = Open coil detected ‘0’
OPENY OPEN Coil Y 1 Status Register 0 ‘1’ = Open coil detected ‘0’
OVCXNB OVer Current on X
H−bridge; MOTXN terminal;
Bottom tran.
1 Status Register 1 ‘0’ = no failure
‘1’ = failure: indicates that over current is
detected at bottom transistor XN−terminal
‘0’
OVCXNT OVer Current on X
H−bridge; MOTXN terminal;
Top transist.
1 Status Register 1 ‘0’ = no failure
‘1’ = failure: indicates that over current is
detected at top transistor XN−terminal
‘0’
OVCXPB OVer Current on X
H−bridge; MOTXP terminal;
Bottom transist.
1 Status Register 1 ‘0’ = no failure
‘1’ = failure: indicates that over current is
detected at bottom transistor XP−terminal
‘0’
OVCXPT OVer Current on X
H−bridge; MOTXP terminal;
Top transist.
1 Status Register 1 ‘0’ = no failure
‘1’ = failure: indicates that over current is
detected at top transistor XP−terminal
‘0’
OVCYNB OVer Current on Y
H−bridge; MOTYN terminal;
Bottom transist.
1 Status Register 2 ‘0’ = no failure
‘1’ = failure: indicates that over current is
detected at bottom transistor YN−terminal
‘0’
OVCYNT OVer Current on Y
H−bridge; MOTYN terminal;
Top transist.
1 Status Register 2 ‘0’ = no failure
‘1’ = failure: indicates that over current is
detected at top transistor YN−terminal
‘0’
OVCYPB OVer Current on Y
H−bridge; MOTYP terminal;
Bottom transist.
1 Status Register 2 ‘0’ = no failure
‘1’ = failure: indicates that over current is
detected at bottom transistor YP−terminal
‘0’
OVCYPT OVer Current on Y
H−bridge; MOTYP terminal;
Top transist.
1 Status Register 2 ‘0’ = no failure
‘1’ = failure: indicates that over current is
detected at top transistor YP−terminal
‘0’
TSD Thermal shutdown 1 Status Register 2 ‘0’
TW Thermal warning 1 Status Register 0 ‘0’
WD Watchdog event (Note 21) 1 Status Register 0 ‘1’ = watchdog reset after time−out ‘0’
21. WD – This bit indicates that the watchdog timer has not been cleared properly. If the master reads that WD is set to “1” after reset, it means
that a watchdog reset occurred (warm boot) instead of POR (cold boot). WD bit will be cleared only when the master writes “0” to WDEN
bit.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P35

AMIS30523C5231G

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Buy AMIS30523C5231G
Manufacturer:
ON Semiconductor
Description:
Motor / Motion / Ignition Controllers & Drivers AMIS30523 MULTI-CHIP ST
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New from this manufacturer.
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