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AMIS30523C5231G

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AMIS−30523
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25
Note: Successive reading the SPI StatusRegisters 1 and 2 in
case of a short circuit condition, may lead to damage to the
drivers
Open Coil/Current Not Reached Detection
Open coil detection is based on the observation of 100%
duty cycle of the PWM regulator. If in a coil 100% duty cycle
is detected for longer than 200 ms then the related driver
transistors are disabled (high−impedance) and an
appropriate bit in the SPI status register is set (<OPENX> or
<OPENY>). (Table 17 SPI Status Register Address SR0)
When the resistance of a motor coil is very large and the
supply voltage is low, it can happen that the motor driver is
not able to deliver the requested current to the motor. Under
these conditions the PWM controller duty cycle will be
100% and after 200 ms the error pin and <OPENX>,
<OPENY> will flag this situation (motor current is kept
alive). This feature can be used to test if the operating
conditions (supply voltage, motor coil resistance) still allow
reaching the requested coil−current or else the coil current
should be reduced.
Charge Pump Failure
The charge pump is an important circuit that guarantees
low R
DS(on)
for all drivers, especially for low supply
voltages. If supply voltage is too low or external components
are not properly connected to guarantee R
DS(on)
of the
drivers, then the bit <CPFAIL> is set in Table 17. Also after
POR the charge pump voltage will need some time to exceed
the required threshold. During that time t
CPU
<CPFAIL>
will be set to “1”.
Error Output
This is a digital output to flag a problem to the external
microcontroller. The signal on this output is active low and
the logic combination of:
NOT(ERRB) = <TW> OR <TSD> OR <OVCXij> OR
< OVCYij> OR <OPENi> OR <CPFAIL>
This open drain output can be wired OR−ed with error
outputs other motor drivers.
Logic Supply Regulator
AMIS−30523 has an on−chip 5 V low−drop regulator
with external capacitor to supply the digital part of the chip,
some low−voltage analog blocks and external circuitry. The
voltage level is derived from an internal bandgap reference.
To calculate the available drive−current for external
circuitry, the specified I
load
should be reduced with the
consumption of internal circuitry (unloaded outputs) and the
loads connected to logic outputs. See Table 5 DC parameters
Motor Driver.
Power−On Reset (POR) Function
The open drain output pin PORB/WD provides an “active
low” reset for external purposes. At power−up of
AMIS−30523, this pin will be kept low for some time to reset
for example an external microcontroller. A small analogue
filter avoids resetting due to spikes or noise on the V
DD
supply.
Figure 22. Power−on−Reset Timing Diagram
VBB
VDD
t
t
V
DDH
V
DDL
POR/WD pin
t
PU
t
PD
< t
RF
t
POR
t
RF
AMIS−30523
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26
Watchdog Function
The watchdog function is enabled/disabled through
<WDEN> bit (See Table 15 SPI Control Registers address
00h). Once this bit has been set to “1” (watchdog enable), the
microcontroller needs to re−write this bit to clear an internal
timer before the watchdog timeout interval expires. In case
the timer is activated and WDEN is acknowledged too early
(before t
WDPR
) or not within the interval (after t
WDTO
), then
a reset of the microcontroller will occur through PORB/WD
pin. In addition, a warm/cold boot bit <WD> is available in
Table 17 for further processing when the external
microcontroller is alive again. See Figure 23.
VBB
VDD
t
t
Enable WD
Acknowledge WD
WD timer
t
t
Figure 23. Watchdog Timing Diagram
V
DDH
t
PU
t
POR
t
DSPI
POR/WD pin
t
WDTO
t
POR
t
WDRD
= t
WDPR
or = t
WDTO
> t
WDPR
and < t
WDTO
NOTE: t
DSPI
is the time needed by the external microcontroller to shift−in the <WDEN> bit after a power−up.
The duration of the watchdog timeout interval is
programmable through the WDT[3:0] bits (See Table 14
SPI Control Registers address 00h). The timing is given in
Table 13 below.
AMIS−30523
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Table 13. WATCHDOG TIMEOUT INTERVAL AS
FUNCTION OF WDT[3.0]
Index WDT[3:0] t
WDTO
(ms)
0 0 0 0 0 32
1 0 0 0 1 64
2 0 0 1 0 96
3 0 0 1 1 128
4 0 1 0 0 160
5 0 1 0 1 192
6 0 1 1 0 224
7 0 1 1 1 256
8 1 0 0 0 288
9 1 0 0 1 320
A 1 0 1 0 352
B 1 0 1 1 384
C 1 1 0 0 416
D 1 1 0 1 448
E 1 1 1 0 480
F 1 1 1 1 512
CLR Pin (= Hard Reset)
Logic 0 on CLR pin allows normal operation of the chip.
To reset the complete digital inside AMIS−30523, the input
CLR needs to be pulled to logic 1 during minimum time
given by t
CLR
. (See Table 6 AC Parameters Motor Driver).
This reset function clears all internal registers without the
need of a power−cycle, except in sleep mode. The operation
of all analog circuits is depending on the reset state of the
digital, charge pump remains active. Logic 0 on CLR pin
resumes normal operation again.
The voltage regulator remains functional during and after
the reset and the PORB/WD pin is not activated. Watchdog
function is reset completely.
Sleep Mode
The bit <SLP> in SPI Control Register 2 (See Table 14
SPI Control Registers address 03h) is provided to enter a
so−called “sleep mode”. This mode allows reduction of
current−consumption when the motor is not in operation.
The effect of sleep mode is as follows:
• The drivers are put in HiZ
• All analog circuits are disabled and in low−power mode
• All internal registers are maintaining their logic content
• NXT and DIR inputs are forbidden
• SPI communication remains possible (slight current
increase during SPI communication)
• Oscillator and digital clocks are silent, except during
SPI communication
The voltage regulator remains active but with reduced
current−output capability (I
LOADSLP
). The watchdog timer
stops running and it’s value is kept in the counter. Upon
leaving sleep mode, this timer continues from the value it
had before entering sleep mode.
Normal operation is resumed after writing logic ‘0’ to bit
<SLP>. A start−up time is needed for the charge pump to
stabilize. After this time, (tcpu) NXT commands can be
issued.
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AMIS30523C5231G

Mfr. #:
Buy AMIS30523C5231G
Manufacturer:
ON Semiconductor
Description:
Motor / Motion / Ignition Controllers & Drivers AMIS30523 MULTI-CHIP ST
Lifecycle:
New from this manufacturer.
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