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AMIS30523C5231G

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AMIS−30523
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28
SPI INTERFACE
The serial peripheral interface (SPI) allows an external
microcontroller (Master) to communicate with
AMIS−30523. The implemented SPI block is designed to
interface directly with numerous micro−controllers from
several manufacturers. AMIS−30523 acts always as a Slave
and can’t initiate any transmission. The operation of the
device is configured and controlled by means of SPI
registers which are observable for read and/or write from the
Master.
SPI Transfer Format and Pin Signals
During a SPI transfer, data is simultaneously transmitted
(shifted out serially) and received (shifted in serially). A
serial clock line (CLK) synchronizes shifting and sampling
of the information on the two serial data lines (DO and DI).
DO signal is the output from the Slave (AMIS−30523), and
DI signal is the output from the Master. A chip select line
(CSB) allows individual selection of a Slave SPI device in
a multiple−slave system. The CSB line is active low. If
AMIS−30523 is not selected, DO is pulled up with the
external pull up resistor. Since AMIS−30523 operates as a
Slave in MODE 0 (CPOL = 0; CPHA = 0) it always clocks
data out on the falling edge and samples data in on rising
edge of clock. The Master SPI port must be configured in
MODE 0 too, to match this operation. The SPI clock idles
low between the transferred bytes.
The diagram below is both a Master and a Slave timing
diagram since CLK, DO and DI pins are directly connected
between the Master and the Slave.
DI
MSB
CLK
1 2 3 4 5 6 7 8
DO
#CLK Cycle
MSB
LSB
LSB
654321
654321
Figure 24. Timing Diagram of a SPI Transfer
CS
NOTE: At the falling edge of the eighth clock pulse the data−out shift register is updated with the content of the addressed internal SPI
register. The internal SPI registers are updated at the first rising edge of the AMIS−30523 system clock when CS
= High.
Transfer Packet:
Serial data transfer is assumed to follow MSB first rule. The transfer packet contains one or more bytes.
LSB
DataCommand and SPI Register Address
CMD2 CMD1 CMD0 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0
D7 D6 D5 D4 D3 D2 D1 D0
MSBLSBMSB
BYTE 1
BYTE 2
Command
SPI Register Address
Figure 25. SPI Transfer Packet
Byte 1 contains the Command and the SPI Register
Address and indicates to AMIS−30523 the chosen type of
operation and addressed register. Byte 2 contains data, or
sent from the Master in a WRITE operation, or received
from AMIS−30523 in a READ operation.
Two command types can be distinguished in the
communication between master and AMIS−30523:
• READ from SPI Register with address ADDR[4:0]:
CMD2 = “0”
AMIS−30523
http://onsemi.com
29
• WRITE to SPI Register with address ADDR[4:0]:
CMD2 = “1”
READ Operation
If the Master wants to read data from Status or Control
Registers, it initiates the communication by sending a
READ command. This READ command contains the
address of the SPI register to be read out. At the falling edge
of the eight clock pulse the data−out shift register is updated
with the content of the corresponding internal SPI register.
In the next 8−bit clock pulse train this data is shifted out via
DO pin. At the same time the data shifted in from DI
(Master) should be interpreted as the following successive
command or dummy data.
Figure 26. Single READ Operation where DATA from SPI Register with Address 1 is Read by the Master
DATA from previous command or
NOT VALID after POR or RESET
Registers are updated with the internal status at the rising edge
of the internal AMIS−30523 clock when CS
= 1
READ DATA from ADDR1 COMMAND or DUMMY
OLD DATA or NOT VALID DATA from ADDR1
COMMAND
DATA DATA
DO
DI
CS
All 4 Status Registers (see Table 17 SPI Registers) contain
7 data bits and a parity check bit The most significant bit
(D7) represents a parity of D[6:0]. If the number of logical
ones in D[6:0] is odd, the parity bit D7 equals “1”. If the
number of logical ones in D[6:0] is even then the parity bit
D7 equals “0”. This simple mechanism protects against
noise and increases the consistency of the transmitted data.
If a parity check error occurs it is recommended to initiate
an additional READ command to obtain the status again.
Also the Control Registers can be read out following the
same routine. Control Registers don’t have a parity check.
The CSB line is active low and may remain low between
successive READ commands as illustrated in Figure 28.
There is however one exception. In case an error condition
is latched in one of Status Registers (see Table 17 SPI
Registers) the ERRB pin is activated. (See the Error Output
section). This signal flags a problem to the external
microcontroller. By reading the Status Registers
information about the root cause of the problem can be
determined. After this READ operation the Status Registers
are cleared. Because the Status Registers and ERRB pin (see
SPI Registers) are only updated by the internal system clock
when the CSB line is high, the Master should force CSB high
immediately after the READ operation. For the same reason
it is recommended to keep the CSB line high always when
the SPI bus is idle.
WRITE Operation
If the Master wants to write data to a Control Register it
initiates the communication by sending a WRITE
command. This contains the address of the SPI register to
write to. The command is followed with a data byte. This
incoming data will be stored in the corresponding Control
Register after CSB goes from low to high! AMIS−30523
responds on every incoming byte by shifting out via DO the
data stored in the last received address.
It is important that the writing action (command − address
and data) to the Control Register is exactly 16 bits long. If
more or less bits are transmitted the complete transfer packet
is ignored (with the exception of preceding read commands
(see Figure 28)).
A WRITE command executed for a read−only register
(e.g. Status Registers) will not affect the addressed register
and the device operation.
Because after a power−on−reset the initial address is
unknown the data shifted out via DO is not valid.
AMIS−30523
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30
DATA from previous command or
NOT VALID after POR or RESET
DO
DI
CS
WRITE DATA to ADDR3 NEW DATA for ADDR3
OLD DATA or NOT VALID
OLD DATA from ADDR3
COMMAND
DATA DATA
DATA
The NEW DATA is written into the corresponding
internal register at the rising edge of CS
Figure 27. Single WRITE Operation where DATA from the Master is Written in SPI Register with Address 3
Examples of Combined READ and WRITE Operations
In the following examples successive READ and WRITE
operations are combined. In Figure 28 the Master first reads
the status from Register at ADDR4 and at ADDR5 followed
by writing a control byte in Control Register at ADDR2.
Note that during the write command the old data of the
pointed register is returned at the moment the new data is
shifted in
Figure 28. Two Successive READ Commands Followed by a WRITE Command
COMMAND
COMMAND COMMAND
DATA
DATA
DATA DATA
DATA
DO
DI
CS
DATA from previous
command or NOT VALID
after POR or RESET
READ DATA
from ADDR4
READ DATA
from ADDR5
WRITE DATA
to ADDR2
NEW DATA
for ADDR2
OLD DATA
or NOT VALID
DATA
from ADDR4
DATA
from ADDR5
OLD DATA
from ADDR2
Registers are updated with the internal status at the rising
edge of the internal 523 clock when CS
= 1
The NEW DATA is written into the corresponding
internal register at the rising edge of CS
After the write operation the Master could initiate a read
back command in order to verify the data correctly written
as illustrated in Figure 29. During reception of the READ
command the old data is returned for a second time. Only
after receiving the READ command the new data is
transmitted. This rule also applies when the master device
wants to initiate an SPI transfer to read the Status Registers.
Because the internal system clock updates the Status
Registers only when CSB line is high, the first read out byte
might represent old status information.
COMMAND
DATA DATA DATA DATA
OLD DATA
or NOT VALID
OLD DATA
from ADDR2
OLD DATA
from ADDR2
NEW DATA
from ADDR2
DO
DI
CS
Figure 29. A WRITE Operation where DATA from the Master is Written in SPI Register with Address 2 Followed by
a READ Back Operation to Verify a Correct WRITE Operation
DATA COMMAND
WRITE DATA
to ADDR2
NEW DATA
for ADDR2
READ DATA
from ADDR2
COMMAND or
DUMMY
Registers are Updated with the Internal
Status at the Rising Edge of CS
Registers are Updated with the In-
ternal Status at the Rising Edge of
the Internal 523 Clock when CS = 1
DATA from previous
command or NOT VALID
after POR or RESET
NOTE: The internal data−out shift buffer of the AMIS−30523 is updated with the content of the selected SPI register only at the last (every
eighth) falling edge of the CLK signal (see SPI Transfer Format and Pin Signals). As a result, new data for transmission cannot be
written to the shift buffer at the beginning of the transfer packet and the first byte shifted out might represent old data.
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AMIS30523C5231G

Mfr. #:
Buy AMIS30523C5231G
Manufacturer:
ON Semiconductor
Description:
Motor / Motion / Ignition Controllers & Drivers AMIS30523 MULTI-CHIP ST
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New from this manufacturer.
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