R8C/3MQ Group 1. Overview
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I: Input O: Output I/O: Input and output
Table 1.7 Pin Functions (2)
Item Pin Name I/O Type Description
Analog power
supply input
VCCRF, VSSRF,
VSSRF1, VSSRF2,
VSS2, DIEGND
Apply the same voltage as the VCC of 1.8 V to 3.6 V to
VCCRF. Apply 0 V to VSSRF, VSSRF1, VSSRF2, VSS2,
and DIEGND.
VREG1 1.5 V IF VDD pin. Connect to the VREGOUT1 pin.
VREG2 1.5 V LNA/MIX/PA VDD pin. Connect to the VREGOUT1 pin.
VREG3
1.5 V PLL ANALOG VDD pin. Connect to the VREGOUT1
pin.
VREG4
1.5 V PLL DIGITAL VDD pin. Connect to the VREGOUT1
pin.
Regulator output VREGOUT1
On-chip regulator output (1.5 V) pin for the analog circuit.
Connect only a bypass capacitor between pins VREGOUT1
and VSS.
Use only as the power supply for pins VREG1, VREG2,
VREG3, and VREGF4.
VREGOUT2
Regulator output (1.5 V) pin for the VCO circuit.
Connect only a bypass capacitor between pins VREGOUT2
and VSS.
Do not use as the power supply for other circuits.
VREGOUT3
Regulator output (1.5 V) pin for the XIN oscillation circuit.
Connect only a bypass capacitor between pins VREGOUT3
and VSS.
Do not use as the power supply for other circuits.
RF I/O RFIOP, RFION I/O RF I/O pins
Test pins IFRXTN, IFRXTP I/O Ports for testing. Leave open or apply 0 V.
External antenna
switch control
output
ASW
O
Signal output pin to control the external antenna switch.
If antenna switch control is not required, leave open.
R8C/3MQ Group 2. Central Processing Unit (CPU)
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2. Central Processing Unit (CPU)
Figure 2.1 shows the CPU Registers. The CPU contains 13 registers. R0, R1, R2, R3, A0, A1, and FB configure a
register bank. There are two sets of register bank.
Figure 2.1 CPU Registers
R2
b31
b15 b8b7
b0
Data registers
(1)
Address registers
(1)
R3
R0H (high-order of R0)
R2
R3
A0
A1
INTBH
b15b19
b0
INTBL
FB
Frame base register
(1)
The 4 high order bits of INTB are INTBH and
the 16 low order bits of INTB are INTBL.
Interrupt table register
b19
b0
USP
Program counter
ISP
SB
User stack pointer
Interrupt stack pointer
Static base register
PC
FLG
Flag register
Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved bit
Processor interrupt priority level
Reserved bit
C
IPL
DZSBOIU
b15
b0
b15
b0
b15
b0
b8
b7
Note:
1. These registers comprise a register bank. There are two register banks.
R1H (high-order of R1)
R0L (low-order of R0)
R1L (low-order of R1)
R8C/3MQ Group 2. Central Processing Unit (CPU)
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2.1 Data Registers (R0, R1, R2, and R3)
R0 is a 16-bit register for transfer, arithmetic, and logic operations. The same applies to R1 to R3. R0 can be split
into high-order bits (R0H) and low-order bits (R0L) to be used separately as 8-bit data registers. R1H and R1L are
analogous to R0H and R0L. R2 can be combined with R0 and used as a 32-bit data register (R2R0). R3R1 is
analogous to R2R0.
2.2 Address Registers (A0 and A1)
A0 is a 16-bit register for address register indirect addressing and address register relative addressing. It is also
used for transfer, arithmetic, and logic operations. A1 is analogous to A0. A1 can be combined with A0 and as a 32-
bit address register (A1A0).
2.3 Frame Base Register (FB)
FB is a 16-bit register for FB relative addressing.
2.4 Interrupt Table Register (INTB)
INTB is a 20-bit register that indicates the starting address of a relocatable interrupt vector table.
2.5 Program Counter (PC)
PC is 20 bits wide and indicates the address of the next instruction to be executed.
2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
The stack pointers (SP), USP and ISP, are each 16 bits wide. The U flag of FLG is used to switch between
USP and ISP.
2.7 Static Base Register (SB)
SB is a 16-bit register for SB relative addressing.
2.8 Flag Register (FLG)
FLG is an 11-bit register indicating the CPU state.
2.8.1 Carry Flag (C)
The C flag retains carry, borrow, or shift-out bits that have been generated by the arithmetic and logic unit.
2.8.2 Debug Flag (D)
The D flag is for debugging only. Set it to 0.
2.8.3 Zero Flag (Z)
The Z flag is set to 1 when an arithmetic operation results in 0; otherwise to 0.
2.8.4 Sign Flag (S)
The S flag is set to 1 when an arithmetic operation results in a negative value; otherwise to 0.
2.8.5 Register Bank Select Flag (B)
Register bank 0 is selected when the B flag is 0. Register bank 1 is selected when this flag is set to 1.
2.8.6 Overflow Flag (O)
The O flag is set to 1 when an operation results in an overflow; otherwise to 0.

R5F213MCQNNP#U0

Mfr. #:
Manufacturer:
Renesas Electronics
Description:
16-bit Microcontrollers - MCU R8CMQ 128+4+7.5KB -20~85C 40WQFN RF4CE
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New from this manufacturer.
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