R5F213MCQNNP#U0 Datasheet R5F213M6QNNP#U0, R5F213M8QNNP#U0, R5F213MAQNNP#U0 | P13-P15

R8C/3MQ Group 2. Central Processing Unit (CPU)

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Jun 29, 2012

2.8.7 Interrupt Enable Flag (I)

The I flag enables maskable interrupts.

Interrupts are disabled when the I flag is set to 0, and are enabled when the I flag is set to 1. The I flag is set to 0

when an interrupt request is acknowledged.

2.8.8 Stack Pointer Select Flag (U)

ISP is selected when the U flag is set to 0; USP is selected when the U flag is set to 1.

The U flag is set to 0 when a hardware interrupt request is acknowledged or the INT instruction of software

interrupt numbers 0 to 31 is executed.

2.8.9 Processor Interrupt Priority Level (IPL)

IPL is 3 bits wide and assigns processor interrupt priority levels from level 0 to level 7.

If a requested interrupt has higher priority than IPL, the interrupt is enabled.

2.8.10 Reserved Bit

If necessary, set to 0. When read, the content is undefined.

R8C/3MQ Group 3. Memory

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3. Memory

3.1 R8C/3MQ Group

Figure 3.1 is a Memory Map of R8C/3MQ Group. The R8C/3MQ Group has a 1-Mbyte address space from

addresses 00000h to FFFFFh. The internal ROM (program ROM) is allocated lower addresses, beginning with

address 0FFFFh. However, for products with internal ROM (program ROM) capacity of 64 Kbytes or more, the

internal ROM is also allocated higher addresses, beginning with address 0FFFFh.

For example, a 32-Kbyte internal ROM area is allocated addresses 08000h to 0FFFFh, and a 96-Kbyte internal

ROM is allocated addresses 04000h to 1BFFFh.

The fixed interrupt vector table is allocated addresses 08000h to 0FFFFh. The starting address of each interrupt

routine is stored here.

The internal ROM (data flash) is allocated addresses 03000h to 03FFFh.

The internal RAM is allocated higher addresses, beginning with address 00400h. For example, a 2.5-Kbyte internal

RAM area is allocated addresses 00400h to 00DFFh. The internal RAM is used not only for data storage but also as

a stack area when a subroutine is called or when an interrupt request is acknowledged.

Special function registers (SFRs) are allocated addresses 00000h to 002FFh and 02C00h to 02FFFh. Peripheral

function control registers are allocated here. All unallocated spaces within the SFRs are reserved and cannot be

accessed by users.

Figure 3.1 Memory Map of R8C/3MQ Group

0FFFFh

0FFDCh

Notes:

1. The data flash indicates block A (1 Kbyte), block B (1 Kbyte), block C (1 Kbyte), and block D (1 Kbyte).

2. The blank areas are reserved and cannot be accessed by users. Do not use the data flash as a program area.

Internal RAM

Size Address 0XXXXh

2.5 Kbytes

4 Kbytes

6 Kbytes

7 Kbytes

7.5 Kbytes

00DFFh

013FFh

01BFFh

01FFFh

021FFh

Part Number

Internal ROM

Size Address 0YYYYh

R5F213M6QNNP

R5F213M7QNNP

R5F213M8QNNP

R5F213MAQNNP

R5F213MCQNNP

32 Kbytes

48 Kbytes

64 Kbytes

96 Kbytes

112 Kbytes

08000h

04000h

Address ZZZZZh

–

13FFFh

1BFFFh

1FFFFh

FFFFFh

0FFFFh

0YYYYh

0XXXXh

00400h

002FFh

00000h

Internal ROM

(program ROM)

Internal RAM

SFR

(Refer to 4. Special Function

Registers (SFRs)

)

02FFFh

02C00h

SFR

(Refer to 4. Special Function

Registers (SFRs)

)

ZZZZZh

03FFFh

03000h

Internal ROM

(data flash)

(1)

Internal ROM

(program ROM)

Undefined instruction

Overflow

BRK instruction

Address match

Single step

Watchdog timer, oscillation stop detection, voltage monitor

Address break

(Reserved)

Reset

0FFD8h

Reserved area

R8C/3MQ Group 4. Special Function Registers (SFRs)

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Jun 29, 2012

4. Special Function Registers (SFRs)

An SFR (special function register) is a control register for a peripheral function. Tables 4.1 to 4.11 list the special

function registers. Table 4.12 lists the ID Code Areas and Option Function Select Area.

X: Undefined

Notes:

1. The blank areas are reserved and cannot be accessed by users.

2. The CWR bit in the RSTFR register is set to 0 after power-on and voltage monitor 0 reset. Hardware reset, software reset, or watchdog timer

reset does not affect this bit.

3. The CSPROINI bit in the OFS register is set to 0.

Table 4.1 SFR Information (1) (0000h to 002Fh)

(1)

Address Register Symbol After Reset

0000h

0001h

0002h

0003h

0004h Processor Mode Register 0 PM0 00h

0005h Processor Mode Register 1 PM1 00h

0006h System Clock Control Register 0 CM0 00101000b

0007h System Clock Control Register 1 CM1 00101000b

0008h Module Standby Control Register MSTCR 00h

0009h System Clock Control Register 3 CM3 00h

000Ah Protect Register PRCR 00h

000Bh Reset Source Determination Register RSTFR

0XXXXXXXb

(2)

000Ch Oscillation Stop Detection Register OCD 00000100b

000Dh Watchdog Timer Reset Register WDTR XXh

000Eh Watchdog Timer Start Register WDTS XXh

000Fh Watchdog Timer Control Register WDTC 00111111b

0010h

0011h

0012h

0013h

0014h

0015h

0016h

0017h

0018h

0019h

001Ah

001Bh

001Ch Count Source Protection Mode Register CSPR 00h

10000000b

(3)

001Dh

001Eh

001Fh

0020h

0021h

0022h

0023h

0024h

0025h

0026h

0027h

0028h Clock Prescaler Reset Flag CPSRF 00h

0029h

002Ah

002Bh

002Ch

002Dh

002Eh

002Fh

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R5F213MCQNNP#U0

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Manufacturer:

Renesas Electronics

Description:

16-bit Microcontrollers - MCU R8CMQ 128+4+7.5KB -20~85C 40WQFN RF4CE

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