SC16C850V All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 5 — 19 January 2011 15 of 48
NXP Semiconductors
SC16C850V
Single UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
6.11 Sleep mode
Sleep mode is an enhanced feature of the SC16C850V UART. It is enabled when EFR[4],
the enhanced functions bit, is set and when IER[4] bit is also set.
6.11.1 Conditions to enter Sleep mode
Sleep mode is entered when:
• Modem input pins are not toggling.
• The serial data input line, RX, is idle for 4 character time (logic HIGH) and AFCR1[4]
is 0. When AFCR1[4] is 1, the device will go to sleep regardless of the state of the RX
pin (see Section 7.21
for the description of AFCR1 bit 4).
• The TX FIFO and TX shift register are empty.
• There are no interrupts pending.
• The RX FIFO is empty.
In Sleep mode, the UART clock and baud rate clock are stopped. Since most registers are
clocked using these clocks, the power consumption is greatly reduced.
Remark: Writing to the divisor latches, DLL and DLM, to set the baud clock, must not be
done during Sleep mode. Therefore, it is advisable to disable Sleep mode using IER[4]
before writing to DLL or DLM.
6.11.2 Conditions to resume normal operation
SC16C850V resumes normal operation by any of the following:
• Receives a start bit on RX pin.
• Data is loaded into transmit FIFO.
• A change of state on any of the modem input pins.
If the device is awakened by one of the conditions described above, it will return to the
Sleep mode automatically after all the conditions described in Section 6.11.1
are met. The
device will stay in Sleep mode until it is disabled by setting any channel’s IER bit 4 to a
logic 0.
When the SC16C850V is in Sleep mode and the host interface bus (AD7 to AD0, IOW
,
IOR
, CS) remains in steady state, either HIGH or LOW, the sleep current will be in the
microampere range as specified in Table 36 “
Static characteristics”. If any of these signals
is toggling or floating then the sleep current will be higher.
6.12 Low power feature
A low power feature is provided by the SC16C850V to prevent the switching of the host
data bus from influencing the sleep current. When the pin LOWPWR is activated (logic
HIGH), the device immediately and unconditionally goes into Low Power mode. All clocks
are stopped and most host interface pins are isolated to reduce power consumption. The
device only returns to normal mode when the LOWPWR pin is de-asserted. The pin can
be left unconnected because it has an internal pull-down resistor.
