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SC16C850VIBS,151

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48
SC16C850V All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 5 — 19 January 2011 34 of 48
NXP Semiconductors
SC16C850V
Single UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
7.23 SC16C850V external reset condition and software reset
These two reset methods are identical and will reset the internal registers as indicated in
Table 33
.
Table 33. Reset state for registers
Register Reset state
IER IER[7:0] = 0
FCR FCR[7:0] = 0
ISR ISR[7:1] = 0; ISR[0] = 1
LCR LCR[7:0] = 0
MCR MCR[7:0] = 0
LSR LSR[7] = 0; LSR[6:5] = 1; LSR[4:0] = 0
MSR MSR[7:4] = input signals; MSR[3:0] = 0
EFCR EFCR[7:0] = 0
SPR SPR[7:0] = 1
DLL undefined
DLM undefined
TXLVLCNT TXLVLCNT[7:0] = 0
RXLVLCNT RXLVLCNT[7:0] = 0
EFR EFR[7:0] = 0
Xon1 Undefined
Xon2 Undefined
Xoff1 Undefined
Xoff2 Undefined
TXINTLVL TXINTLVL[7:0] = 0
RXINTLVL RXINTLVL[7:0] = 0
FLWCNTH FLWCNTH[7:0] = 0
FLWCNTL FLWCNTL[7:0] = 0
CLKPRES CLKPRES[7:0] = 0
RS485TIME RS485TIME[7:0] = 0
AFCR2 AFCR2[7:0] = 0
AFCR1 AFCR1[7:0] = 0
Table 34. Reset state for outputs
Output Reset state
TX logic 1
RTS
logic 1
DTR
logic 1
INT 3-state condition
SC16C850V All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 5 — 19 January 2011 35 of 48
NXP Semiconductors
SC16C850V
Single UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
8. Limiting values
[1] V
n
should not exceed 2.5 V.
9. Static characteristics
[1] Hysteresis input.
[2] Except XTAL2.
[3] Sleep current might be higher if there is any activity on the UART data bus during Sleep mode.
[4] Activate by LOWPWR pin.
Table 35. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
V
DD
supply voltage - 2.5 V
V
n
voltage on any other pin
[1]
V
SS
− 0.3 V
DD
+0.3 V
T
amb
ambient temperature operating in free air −40 +85 °C
T
stg
storage temperature −65 +150 °C
P
tot
/pack total power dissipation per
package
-500mW
Table 36. Static characteristics
T
amb
=
−
40
°
C to +85
°
C; V
DD
= 1.65 V to 1.95 V; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
V
IL(clk)
clock LOW-level input
voltage
XTAL1 pin - - 0.25 V
V
IH(clk)
clock HIGH-level input
voltage
XTAL1 pin 1.35 - - V
V
IL
LOW-level input voltage except XTAL1 clock,
LOWPWR pin
--0.45V
LOWPWR pin
[1]
--0.45V
V
IH
HIGH-level input voltage except XTAL1 clock,
LOWPWR pin
1.35 - - V
LOWPWR pin
[1]
1.35 - - V
V
OL
LOW-level output voltage I
OL
=2mA
[2]
--0.35V
V
OH
HIGH-level output voltage I
OH
= −800 μA
[2]
1.45 - - V
I
LIL
LOW-level input leakage
current
--1μA
I
LIH
HIGH-level input leakage
current
--1μA
I
L(clk)
clock leakage current LOW-level - - 30 μA
HIGH-level - - 30 μA
I
DD
supply current f = 5 MHz - - 2 mA
I
DD(sleep)
sleep mode supply current
[3]
--5μA
I
DD(lp)
low-power mode supply
current
[4]
--5μA
C
i
input capacitance - - 5 pF
SC16C850V All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 5 — 19 January 2011 36 of 48
NXP Semiconductors
SC16C850V
Single UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
10. Dynamic characteristics
[1] External clock only; maximum crystal frequency is 24 MHz.
[2] 10 % of the data bus output voltage level.
[3] RCLK is an internal frequency and it is equal to 16 times the baud rate.
Table 37. Dynamic characteristics
T
amb
=
−
40
°
C to +85
°
C; V
DD
= 1.65 V to 1.95 V; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
f
XTAL1
frequency on pin XTAL1
[1]
--80MHz
t
d(CS-LLAH)
delay time from CS to LLA HIGH 10 - - ns
t
su(A-LLAH)
set-up time from address to LLA HIGH 5 - - ns
t
w(LLA)
LLA pulse width time 10 - - ns
t
h(LLAH-A)
address hold time after LLA HIGH 10 - - ns
t
d(IOW)
IOW delay time 10 - - ns
t
d(IOR-DV)
delay time from IOR to data valid 25 pF load - - 40 ns
t
w(IOR)
IOR pulse width time 20 - - ns
t
d(LLAH-IORL)
delay time from LLA HIGH to IOR LOW 10 - - ns
t
w(IOW)
IOW pulse width time 10 - - ns
t
h(IOWH-D)
data input hold time after IOW HIGH 5 - - ns
t
d(LLAH-IOWL)
delay time from LLA HIGH to IOW LOW 10 - - ns
t
su(D-IOWH)
set-up time from data input to IOW HIGH 5 - - ns
t
d(IOR)
IOR delay time 10 - - ns
t
dis(IOR-QZ)
disable time from IOR to high-impedance data
output
[2]
25 pF load - - 20 ns
t
d(IOW-Q)
delay time from IOW to data output 25 pF load - - 50 ns
t
d(modem-INT)
delay time from modem to INT 25 pF load - - 50 ns
t
d(IOR-INTL)
delay time from IOR to INT LOW 25 pF load - - 50 ns
t
WH
pulse width HIGH 6 - - ns
t
WL
pulse width LOW 6 - - ns
t
w(clk)
clock pulse width 12.5 - - ns
t
d(stop-INT)
delay time from stop to INT 25 pF load
[3]
--1T
RCLK
s
t
d(start-INT)
delay time from start to INT 25 pF load
[3]
--1T
RCLK
s
t
d(IOW-TX)
delay time from IOW to TX
[3]
8T
RCLK
- 24T
RCLK
s
t
d(IOW-INTL)
delay time from IOW to INT LOW 25 pF load - - 50 ns
t
w(RESET_N)
pulse width on pin RESET 10 - - ns
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SC16C850VIBS,151

Mfr. #:
Buy SC16C850VIBS,151
Manufacturer:
NXP Semiconductors
Description:
IC UART SINGLE W/FIFO 32-HVQFN
Lifecycle:
New from this manufacturer.
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