SC16C850VIBS,151 Datasheet SC16C850VIBS,115, SC16C850VIBS,128, SC16C850VIBS,151 | P7-P9

Product data sheet Rev. 5 — 19 January 2011 7 of 48

NXP Semiconductors

SC16C850V

Single UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface

6.2 Extended mode (128-byte FIFO)

The device is in the extended mode when any of these four registers contains any value

other than 0: FLWCNTH, FLWCNTL, TXINTLVL, RXINTLVL.

6.3 Internal registers

The SC16C850V provides a set of 25 internal registers for monitoring and controlling the

functions of the UART. These registers are shown in Table 4

[1] These registers are accessible only when LCR[7] is a logic 0.

[2] These registers are accessible only when LCR[7] is a logic 1.

Table 4. Internal registers decoding

A3 A2 A1 Read mode Write mode

General register set (THR/RHR, IER/ISR, MCR/MSR, FCR, LSR, SPR)

[1]

000Receive Holding Register Transmit Holding Register

001Interrupt Enable Register Interrupt Enable Register

010Interrupt Status Register FIFO Control Register

011Line Control Register Line Control Register

100Modem Control Register Modem Control Register

101Line Status Register Extra Feature Control Register (EFCR)

110Modem Status Register n/a

111Scratchpad Register Scratchpad Register

Baud rate register set (DLL/DLM)

[2]

000LSB of Divisor Latch LSB of Divisor Latch

001MSB of Divisor Latch MSB of Divisor Latch

Second special register set (TXLVLCNT/RXLVLCNT)

[3]

011Transmit FIFO Level Count n/a

100Receive FIFO Level Count n/a

Enhanced register set (EFR, Xon1/Xon2, Xoff1/Xoff2)

[4]

010Enhanced Feature Register Enhanced Feature Register

100Xon1 word Xon1 word

101Xon2 word Xon2 word

110Xoff1 word Xoff1 word

111Xoff2 word Xoff2 word

First extra feature register set (TXINTLVL/RXINTLVL, FLWCNTH/FLWCNTL)

[5]

010Transmit FIFO Interrupt Level Transmit FIFO Interrupt Level

100Receive FIFO Interrupt Level Receive FIFO Interrupt Level

110Flow Control Count High Flow Control Count High

111Flow Control Count Low Flow Control Count Low

Second extra feature register set (CLKPRES, RS485TIME, AFCR2, AFCR1)

[6]

0 1 0 Clock Prescaler Clock Prescaler

100RS-485 turn-around Timer RS-485 turn-around Timer

110Additional Feature Control Register 2Additional Feature Control Register 2

111Additional Feature Control Register 1Additional Feature Control Register 1

Product data sheet Rev. 5 — 19 January 2011 8 of 48

NXP Semiconductors

SC16C850V

Single UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface

[3] Second special registers are accessible only when EFCR[0] = 1.

[4] Enhanced Feature Registers are only accessible when LCR = 0xBF.

[5] First extra feature registers are only accessible when EFCR[2:1] = 01b.

[6] Second extra feature registers are only accessible when EFCR[2:1] = 10b.

6.4 FIFO operation

6.4.1 32-byte FIFO mode

When all four of these registers (TXINTLVL, RXINTLVL, FLWCNTH, FLWCNTL) in the

First Extra Register Set are empty (0x00) the transmit and receive trigger levels are set by

FCR[7:4]. In this mode the transmit and receive trigger levels are backward compatible to

the SC16C650B (see Table 5

), and the FIFO sizes are 32 entries. The transmit and

receive data FIFOs are enabled by the FIFO Control Register bit 0 (FCR[0]). It should be

noted that the user can set the transmit trigger levels by writing to the FCR, but activation

will not take place until EFR[4] is set to a logic 1. The receiver FIFO section includes a

time-out function to ensure data is delivered to the external CPU (see Section 6.8

). Please

refer to Table 10

and Table 11 for the setting of FCR[7:4].

6.4.2 128-byte FIFO mode

When either TXINTLVL, RXINTLVL, FLWCNTH or FLWCNTL in the First Extra Register

Set contains any value other than 0x00, the transmit and receive trigger levels are set by

TXINTLVL and RXINTLVL registers. TXINTLVL sets the trigger levels for the transmit

FIFO, and the transmit trigger levels can be set to any value between 1 and 128 with

granularity of 1. RXINTLVL sets the trigger levels for the receive FIFO, the receive trigger

levels can be set to any value between 1 and 128 with granularity of 1.

When the effective FIFO size changes (that is, when FCR[0] toggles or when the

combined content of TXINTLVL, RXINTLVL, FLWCNTH and FLWCNTL changes between

equal and unequal to 0x00), both RX FIFO and TX FIFO will be reset (data in the FIFO will

be lost).

6.5 Hardware flow control

When automatic hardware flow control is enabled, the SC16C850V monitors the CTS pin

for a remote buffer overflow indication and controls the RTS

pin for local buffer overflows.

Automatic hardware flow control is selected by setting EFR[6] (RTS) and EFR[7] (CTS) to

a logic 1. If CTS

transitions from a logic 0 to a logic 1 indicating a flow control request,

ISR[5] will be set to a logic 1 (if enabled via IER[7:6]), and the SC16C850V will suspend

TX transmissions as soon as the stop bit of the character in process is shifted out.

Transmission is resumed after the CTS

input returns to a logic 0, indicating more data

may be sent.

Table 5. Interrupt trigger level and Flow control mechanism

FCR[7:6] FCR[5:4] INT pin activation Negate RTS or

send Xoff

Assert RTS

or send Xon

RX TX

00008168 0

01 01 16 8 16 7

10 10 24 24 24 15

11 11 28 30 28 23

Product data sheet Rev. 5 — 19 January 2011 9 of 48

NXP Semiconductors

SC16C850V

Single UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface

When AFCR1[2] is set to 1, then the function of CTS pin is mapped to the DSR pin, and

the function of RTS

is mapped to DTR pin. DSR and DTR pins will behave as described

above for CTS

and RTS.

With the automatic hardware flow control function enabled, an interrupt is generated when

the receive FIFO reaches the programmed trigger level. The RTS

(or DTR) pin will not be

forced to a logic 1 (RTS off) until the receive FIFO reaches the next trigger level. However,

the RTS

(or DTR) pin will return to a logic 0 after the receive buffer (FIFO) is unloaded to

the next trigger level below the programmed trigger level. Under the above described

conditions, the SC16C850V will continue to accept data until the receive FIFO is full.

When TXINTLVL, RXINTLVL, FLWCNTH and FLWCNTL in the First Extra Register Set

are all zeroes, the hardware and software flow control trigger levels are set by FCR[7:4];

see Table 5

When either TXINTLVL, RXINTLVL, FLWCNTH or FLWCNTL in the First Extra Register

Set contains any value other than 0x00, the hardware and software flow control trigger

levels are set by FLWCNTH and FLWCNTL. The content in FLWCNTH determines how

many bytes are in the receive FIFO before RTS

(or DTR) is de-asserted or Xoff is sent.

The content of FLWCNTL determines how many bytes are in the receive FIFO before

RTS

(or DTR) is asserted, or Xon is sent.

In 128-byte FIFO mode, hardware and software flow control trigger levels can be set to

any value between 1 and 128 in granularity of 1. The value of FLWCNTH should always

be greater than FLWCNTL. The UART does not check for this condition automatically, and

if this condition is not met spurious operation of the device might occur. When using

FLWCNTH and FWLCNTL, these registers must be initialized to the proper values before

hardware or software flow control is enabled via the EFR register.

6.6 Software flow control

When software flow control is enabled, the SC16C850V compares one or two sequentially

received data characters with the programmed Xon or Xoff character value(s). If the

received character(s) match the programmed Xoff values, the SC16C850V will halt

transmission (TX) as soon as the current character(s) has completed transmission. When

a match occurs, ISR bit 4 will be set (if enabled via IER[5]) and the interrupt output pin (if

receive interrupt is enabled) will be activated. Following a suspension due to a match of

the Xoff characters’ values, the SC16C850V will monitor the receive data stream for a

match to the Xon1/Xon2 character value(s). If a match is found, the SC16C850V will

resume operation and clear the flags (ISR[4]).

Reset initially sets the contents of the Xon/Xoff 8-bit flow control registers to a logic 0.

Following reset, the user can write any Xon/Xoff value desired for software flow control.

Different conditions can be set to detect Xon/Xoff characters and suspend/resume

transmissions (see Table 24

). When double 8-bit Xon/Xoff characters are selected, the

SC16C850V compares two consecutive receive characters with two software flow control

8-bit values (Xon1, Xon2, Xoff1, Xoff2) and controls TX transmissions accordingly. Under

the above described flow control mechanisms, flow control characters are not placed

(stacked) in the receive FIFO. When using software flow control, the Xon/Xoff characters

cannot be used for data transfer.

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SC16C850VIBS,151

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NXP Semiconductors

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IC UART SINGLE W/FIFO 32-HVQFN

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SC16C850VIBS,151

SC16C850VIBS,151

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