SC16C850V All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 5 — 19 January 2011 32 of 48
NXP Semiconductors
SC16C850V
Single UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
7.20 RS-485 turn-around time delay (RS485TIME)
The value in this register controls the turn-around time of the external line transceiver in
bit time. In automatic 9-bit mode, the RTS
or DTR pin is used to control the direction of the
line driver, after the last bit of data has been shifted out of the transmit shift register the
UART will count down the value in this register. When the count value reaches zero, the
UART will assert the RTS
or DTR pin (logic 0) to turn the external RS-485 transceiver
around for receiving.
7.21 Advanced Feature Control Register 1 (AFCR1)
[1] It takes 4 XTAL1 clocks to reset the device.
Table 30. RS-485 programmable turn-around time register
Bit Symbol Description
7:0 RS485TIME[7:0] External RS-485 transceiver turn-around time delay. The value
represents the bit time at the programmed baud rate.
Table 31. Advanced Feature Control Register 1 bits description
Bit Symbol Description
7:5 AFCR1[7:5] reserved
4 AFCR1[4] Sleep RXlow. Program RX input to be edge-sensitive or level-sensitive.
logic 0 = RX input is level sensitive. If RX pin is LOW, the UART will not
go to sleep. Once the UART is in Sleep mode, it will wake up if RX pin
goes LOW.
logic 1 = RX input is edge sensitive. UART will go to sleep even if RX pin
is LOW, and will wake up when RX pin toggles.
3 AFCR1[3] reserved
2 AFCR1[2] RTS/CTS mapped to DTR/DSR. Switch the function of RTS/CTS to
DTR/DSR.
logic 0 = RTS and CTS signals are used for hardware flow control
logic 1 = DTR and DSR signals are used for hardware flow control. RTS
and CTS retain their functionality.
1 AFCR1[1] SReset. Software reset. A write to this bit will reset the UART. Once the
UART is reset this bit is automatically set to logic 0.
[1]
0 AFCR1[0] TSR interrupt. Select TSR interrupt mode.
logic 0 = transmit empty interrupt occurs when transmit FIFO falls below
the trigger level or becomes empty.
logic 1 = transmit empty interrupt occurs when transmit FIFO fall below
the trigger level, or becomes empty and the last stop bit has been shift
out the transmit shift register.
