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SC16C850VIBS,151

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48
SC16C850V All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 5 — 19 January 2011 22 of 48
NXP Semiconductors
SC16C850V
Single UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
7.3 FIFO Control Register (FCR)
This register is used to enable the FIFOs, clear the FIFOs and set the receive FIFO trigger
levels.
7.3.1 FIFO mode
[1] For 128-byte FIFO mode, refer to Section 7.16, Section 7.17, Section 7.18.
[2] For 128-byte FIFO mode, refer to Section 7.15
, Section 7.17, Section 7.18.
[1] When RXINTLVL or TXINTLVL or FLWCNTH or FLWCNTL contains any value other than 0x00, receive and
transmit trigger levels are set by RXINTLVL, TXINTLVL; see Section 6.4 “
FIFO operation”.
Table 9. FIFO Control Register bits description
Bit Symbol Description
7:6 FCR[7:6] Receive trigger level in 32-byte FIFO mode.
[1]
These bits are used to set the trigger level for receive FIFO interrupt and flow
control. The SC16C850V will issue a receive ready interrupt when the number
of characters in the receive FIFO reaches the selected trigger level. Refer to
Table 10
.
5:4 FCR[5:4] Transmit trigger level in 32-byte FIFO mode.
[2]
These bits are used to set the trigger level for the transmit FIFO interrupt and
flow control. The SC16C850V will issue a transmit empty interrupt when the
number of characters in FIFO drops below the selected trigger level. Refer to
Table 11
.
3 FCR[3] reserved
2 FCR[2] XMIT FIFO reset.
logic 0 = no FIFO transmit reset (normal default condition)
logic 1 = clears the contents of the transmit FIFO and resets the FIFO
counter logic. This bit will return to a logic 0 after clearing the FIFO.
1 FCR[1] RCVR FIFO reset.
logic 0 = no FIFO receive reset (normal default condition)
logic 1 = clears the contents of the receive FIFO and resets the FIFO
counter logic. This bit will return to a logic 0 after clearing the FIFO.
0 FCR[0] FIFO enable.
logic 0 = disable the transmit and receive FIFO (normal default condition)
logic 1 = enable the transmit and receive FIFO
Table 10. RCVR trigger levels
FCR[7] FCR[6] RX FIFO trigger level in 32-byte FIFO mode
[1]
0 0 8 bytes
0 1 16 bytes
1 0 24 bytes
1 1 28 bytes
SC16C850V All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 5 — 19 January 2011 23 of 48
NXP Semiconductors
SC16C850V
Single UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
[1] When RXINTLVL or TXINTLVL or FLWCNTH or FLWCNTL contains any value other than 0x00, receive and
transmit trigger levels are set by RXINTLVL, TXINTLVL; see Section 6.4 “
FIFO operation”.
7.4 Interrupt Status Register (ISR)
The SC16C850V provides six levels of prioritized interrupts to minimize external software
interaction. The Interrupt Status Register (ISR) provides the user with six interrupt status
bits. Performing a read cycle on the ISR will provide the user with the highest pending
interrupt level to be serviced. No other interrupts are acknowledged until the pending
interrupt is serviced. A lower level interrupt may be seen after servicing the higher level
interrupt and re-reading the interrupt status bits. Table 12 “
Interrupt source” shows the
data values (bits 5:0) for the six prioritized interrupt levels and the interrupt sources
associated with each of these interrupt levels.
Table 11. TX FIFO trigger levels
FCR[5] FCR[4] TX FIFO trigger level in 32-byte FIFO mode
[1]
0 0 16 bytes
0 1 8 bytes
1 0 24 bytes
1 1 30 bytes
Table 12. Interrupt source
Priority
level
ISR[5] ISR[4] ISR[3] ISR[2] ISR[1] ISR[0] Source of the interrupt
1 000110LSR (Receiver Line Status Register)
2 000100RXRDY (Received Data Ready)
2 001100RXRDY (Receive Data time-out)
3 000010TXRDY (Transmitter Holding
Register Empty)
4 000000MSR (Modem Status Register)
5 010000RXRDY (Received Xoff signal)/
Special character
6 100000CTS, RTS change of state
Table 13. Interrupt Status Register bits description
Bit Symbol Description
7:6 ISR[7:6] FIFOs enabled. These bits are set to a logic 0 when the FIFOs are not being
used in the non-FIFO mode. They are set to a logic 1 when the FIFOs are
enabled in the SC16C850V mode.
logic 0 or cleared = default condition
5:4 ISR[5:4] INT priority bits 4:3. These bits are enabled when EFR[4] is set to a logic 1.
ISR[4] indicates that matching Xoff character(s) have been detected. ISR[5]
indicates that CTS, RTS have been generated. Note that once set to a
logic 1, the ISR[4] bit will stay a logic 1 until Xon character(s) are received.
logic 0 or cleared = default condition
3:1 ISR[3:1] INT priority bits 2:0. These bits indicate the source for a pending interrupt at
interrupt priority levels 1, 2, and 3 (see Table 12
).
logic 0 or cleared = default condition
SC16C850V All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 5 — 19 January 2011 24 of 48
NXP Semiconductors
SC16C850V
Single UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
7.5 Line Control Register (LCR)
The Line Control Register is used to specify the asynchronous data communication
format. The word length, the number of stop bits, and the parity are selected by writing the
appropriate bits in this register.
0 ISR[0] INT status.
logic 0 = an interrupt is pending and the ISR contents may be used as a
pointer to the appropriate interrupt service routine
logic 1 = no interrupt pending (normal default condition)
Table 13. Interrupt Status Register bits description
…continued
Bit Symbol Description
Table 14. Line Control Register bits description
Bit Symbol Description
7 LCR[7] Divisor latch enable. The internal baud rate counter latch and Enhanced
Feature mode enable.
logic 0 = divisor latch disabled (normal default condition)
logic 1 = divisor latch enabled
6 LCR[6] Set break. When enabled, the Break control bit causes a break condition to be
transmitted (the TX output is forced to a logic 0 state). This condition exists
until disabled by setting LCR[6] to a logic 0.
logic 0 = no TX break condition (normal default condition)
logic 1 = forces the transmitter output (TX) to a logic 0 for alerting the
remote receiver to a line break condition
5:3 LCR[5:3] Programs the parity conditions (see Table 15
).
2 LCR[2] Stop bits. The length of stop bit is specified by this bit in conjunction with the
programmed word length (see Table 16
).
logic 0 or cleared = default condition
1:0 LCR[1:0] Word length bits 1, 0. These two bits specify the word length to be transmitted
or received (see Table 17
).
logic 0 or cleared = default condition
Table 15. LCR[5:3] parity selection
LCR[5] LCR[4] LCR[3] Parity selection
X X 0 no parity
X 0 1 odd parity
011even parity
001forced parity ‘1’
111forced parity ‘0’
Table 16. LCR[2] stop bit length
LCR[2] Word length (bits) Stop bit length (bit times)
0 5, 6, 7, 8 1
15 1
1
⁄
2
1 6, 7, 8 2
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48

SC16C850VIBS,151

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Buy SC16C850VIBS,151
Manufacturer:
NXP Semiconductors
Description:
IC UART SINGLE W/FIFO 32-HVQFN
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