2010-2015 Microchip Technology Inc. DS30009622M-page 13
PIC18F2XXX/4XXX FAMILY
In addition to the code memory space, there are three blocks that are accessible to the user through Table Reads and
Table Writes. Their locations in the memory map are shown in Figure 2-12.
Users may store identification information (ID) in eight ID registers. These ID registers are mapped in addresses, 200000h
through 200007h. The ID locations read out normally, even after code protection is applied.
Locations, 300000h through 30000Dh, are reserved for the Configuration bits. These bits select various device options
and are described in Section 5.0 “Configuration Word”. These Configuration bits read out normally, even after code
protection.
Locations, 3FFFFEh and 3FFFFFh, are reserved for the Device ID bits. These bits may be used by the programmer to
identify what device type is being programmed and are described in Section 5.0 “Configuration Word”. These Device
ID bits read out normally, even after code protection.
2.3.1 MEMORY ADDRESS POINTER
Memory in the address space, 0000000h to 3FFFFFh, is addressed via the Table Pointer register, which is comprised
of three pointer registers:
• TBLPTRU at RAM address 0FF8h
• TBLPTRH at RAM address 0FF7h
• TBLPTRL at RAM address 0FF6h
The 4-bit command, ‘0000’ (core instruction), is used to load the Table Pointer prior to using many read or write
operations.
TBLPTRU TBLPTRH TBLPTRL
Addr[21:16] Addr[15:8] Addr[7:0]
