2010-2015 Microchip Technology Inc. DS30009622M-page 19
PIC18F2XXX/4XXX FAMILY
FIGURE 2-18: TABLE WRITE, POST-INCREMENT TIMING (1101)
2.8 Dedicated ICSP/ICD Port (44-Pin TQFP Only)
The PIC18F4455/4458/4550/4553 44-pin TQFP devices are designed to support an alternate programming input: the
dedicated ICSP/ICD port. The primary purpose of this port is to provide an alternate In-Circuit Debugging (ICD) option
and free the pins (RB6, RB7 and MCLR) that would normally be used for debugging the application. In conjunction with
ICD capability, however, the dedicated ICSP/ICD port also provides an alternate port for ICSP.
Setting the ICPRT Configuration bit enables the dedicated ICSP/ICD port. The dedicated ICSP/ICD port functions the
same as the default ICSP/ICD port; however, alternate pins are used instead of the default pins. Table 2-10 identifies
the functionally equivalent pins for ICSP purposes:
The dedicated ICSP/ICD port is an alternate port. Thus, ICSP is still available through the default port even though the
ICPRT Configuration bit is set. When the V
IH is seen on the MCLR/VPP/RE3 pin prior to applying VIH to the ICRST/ICVPP
pin, then the state of the ICRST/ICVPP pin is ignored. Likewise, when the VIH is seen on ICRST/ICVPP prior to applying
V
IH to MCLR/VPP/RE3, then the state of the MCLR/VPP/RE3 pin is ignored.
TABLE 2-10: ICSP™ EQUIVALENT PINS
Note: The ICPRT Configuration bit can only be programmed through the default ICSP port. Chip Erase functions
through the dedicated ICSP/ICD port do not affect this bit.
When the ICPRT Configuration bit is set (dedicated ICSP/ICD port enabled), the NC/ICPORTS pin must
be tied to either V
DD or VSS.
The ICPRT Configuration bit must be maintained clear for all 28-pin and 40-pin devices; otherwise,
unexpected operation may occur.
Pin Name
During Programming
Pin Name Pin Type Dedicated Pins Pin Description
MCLR
/VPP/RE3 VPP P NC/ICRST/ICVPP Programming Enable
RB6 PGC I NC/ICCK/ICPGC Serial Clock
RB7 PGD I/O NC/ICDT/ICPGD Serial Data
Legend: I = Input, O = Output, P = Power
1234
PGC
P5
PGD
PGD = Input
5678
1
234
P5A
9
10 11 13 15 161412
Fetch Next 4-Bit Command
1011
1234
nnnn
P3
P2
P2A
000000 010001111 0
04C3
P4
4-Bit Command 16-Bit Data Payload
P2B
PIC18F2XXX/4XXX FAMILY
DS30009622M-page 20 2010-2015 Microchip Technology Inc.
3.0 DEVICE PROGRAMMING
Programming includes the ability to erase or write the various memory regions within the device.
In all cases, except high-voltage ICSP Bulk Erase, the EECON1 register must be configured in order to operate on a
particular memory region.
When using the EECON1 register to act on code memory, the EEPGD bit must be set (EECON1<7> = 1) and the CFGS
bit must be cleared (EECON1<6> = 0). The WREN bit must be set (EECON1<2> = 1) to enable writes of any sort (e.g.,
erases) and this must be done prior to initiating a write sequence. The FREE bit must be set (EECON1<4> = 1) in order
to erase the program space being pointed to by the Table Pointer. The erase or write sequence is initiated by setting the
WR bit (EECON1<1> = 1). It is strongly recommended that the WREN bit only be set immediately prior to a program
erase.
3.1 ICSP Erase
3.1.1 HIGH-VOLTAGE ICSP BULK ERASE
Erasing code or data EEPROM is accomplished by configuring two Bulk Erase Control registers located at 3C0004h
and 3C0005h. Code memory may be erased, portions at a time, or the user may erase the entire device in one action.
Bulk Erase operations will also clear any code-protect settings associated with the memory block being erased. Erase
options are detailed in Table 3-1. If data EEPROM is code-protected (CPD = 0), the user must request an erase of data
EEPROM (e.g., 0084h as shown in Table 3-1).
TABLE 3-1: BULK ERASE OPTIONS
The actual Bulk Erase function is a self-timed operation. Once the erase has started (falling edge of the 4th PGC after
the NOP command), serial execution will cease until the erase completes (Parameter P11). During this time, PGC may
continue to toggle but PGD must be held low.
The code sequence to erase the entire device is shown in Table and the flowchart is shown in Figure 3-1.
Description
Data
(3C0005h:3C0004h)
Chip Erase 3F8Fh
Erase Data EEPROM
(1)
0084h
Erase Boot Block 0081h
Erase Configuration Bits 0082h
Erase Code EEPROM Block 0 0180h
Erase Code EEPROM Block 1 0280h
Erase Code EEPROM Block 2 0480h
Erase Code EEPROM Block 3 0880h
Erase Code EEPROM Block 4 1080h
Erase Code EEPROM Block 5 2080h
Note 1: Selected devices only, see Section 3.3 “Data EEPROM Programming”.
Note: A Bulk Erase is the only way to reprogram code-protect bits from an ON state to an OFF state.
2010-2015 Microchip Technology Inc. DS30009622M-page 21
PIC18F2XXX/4XXX FAMILY
FIGURE 3-1: BULK ERASE FLOW
TABLE 3-2: BULK ERASE COMMAND SEQUENCE
4-Bit Command Data Payload Core Instruction
0000
0000
0000
0000
0000
0000
1100
0000
0000
0000
0000
0000
0000
1100
0000
0000
0E 3C
6E F8
0E 00
6E F7
0E 05
6E F6
3F 3F
0E 3C
6E F8
0E 00
6E F7
0E 04
6E F6
8F 8F
00 00
00 00
MOVLW 3Ch
MOVWF TBLPTRU
MOVLW 00h
MOVWF TBLPTRH
MOVLW 05h
MOVWF TBLPTRL
Write 3F3Fh to 3C0005h
MOVLW 3Ch
MOVWF TBLPTRU
MOVLW 00h
MOVWF TBLPTRH
MOVLW 04h
MOVWF TBLPTRL
Write 8F8Fh TO 3C0004h to erase entire device.
NOP
Hold PGD low until erase completes.
Start
Done
Write 8F8Fh to
3C0004h to Erase
Entire Device
Write 3F3Fh
Delay P11 + P10
Time
to 3C0005h

PIC18F4510-E/ML

Mfr. #:
Manufacturer:
Microchip Technology
Description:
8-bit Microcontrollers - MCU 32KB 1536 RAM 36I/O
Lifecycle:
New from this manufacturer.
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