PIC18F4510-E/ML Datasheet PIC18F4321-I/PT, PIC18F4410-I/PT, PIC18F4510-I/PT | P22-P24

PIC18F2XXX/4XXX FAMILY

DS30009622M-page 22  2010-2015 Microchip Technology Inc.

3.1.2 LOW-VOLTAGE ICSP BULK ERASE

When using low-voltage ICSP, the part must be supplied by the voltage specified in Parameter D111 if a Bulk Erase is

to be executed. All other Bulk Erase details, as described above, apply.

If it is determined that a program memory erase must be performed at a supply voltage below the Bulk Erase limit, refer

to the erase methodology described in Section 3.1.3 “ICSP Row Erase” and Section 3.2.1 “Modifying Code

Memory”.

If it is determined that a data EEPROM erase (selected devices only, see Section 3.3 “Data EEPROM

Programming”) must be performed at a supply voltage below the Bulk Erase limit, follow the methodology described

in Section 3.3 “Data EEPROM Programming” and write ‘1’s to the array.

FIGURE 3-2: BULK ERASE TIMING

3.1.3 ICSP ROW ERASE

Regardless of whether high or low-voltage ICSP is used, it is possible to erase one row (64 bytes of data), provided the block

is not code or write-protected. Rows are located at static boundaries, beginning at program memory address, 000000h,

extending to the internal program memory limit (see Section 2.3 “Memory Maps”).

The Row Erase duration is externally timed and is controlled by PGC. After the WR bit in EECON1 is set, a NOP is

issued, where the 4th PGC is held high for the duration of the programming time, P9.

After PGC is brought low, the programming sequence is terminated. PGC must be held low for the time specified by

Parameter P10 to allow high-voltage discharge of the memory array.

The code sequence to Row Erase a PIC18F2XXX/4XXX Family device is shown in Table 3-3. The flowchart, shown in

Figure 3-3, depicts the logic necessary to completely erase a PIC18F2XXX/4XXX Family device. The timing diagram

that details the Start Programming command and Parameters P9 and P10 is shown in Figure 3-5.

Note: The TBLPTR register can point to any byte within the row intended for erase.

1234

21516 123

PGC

P5A

PGD

PGD = Input

0011

P11

P10

Erase Time

0000

1 2 15 16

123

P5A

0000

4-Bit Command

16-Bit

Data Payload

16-Bit

Data Payload

16-Bit

Data Payload

 2010-2015 Microchip Technology Inc. DS30009622M-page 23

PIC18F2XXX/4XXX FAMILY

TABLE 3-3: ERASE CODE MEMORY CODE SEQUENCE

FIGURE 3-3: SINGLE ROW ERASE CODE MEMORY FLOW

4-Bit

Command

Data Payload Core Instruction

Step 1: Direct access to code memory and enable writes.

0000

8E A6

9C A6

84 A6

BSF EECON1, EEPGD

BCF EECON1, CFGS

BSF EECON1, WREN

Step 2: Point to first row in code memory.

0000

6A F8

6A F7

6A F6

CLRF TBLPTRU

CLRF TBLPTRH

CLRF TBLPTRL

Step 3: Enable erase and erase single row.

0000

88 A6

82 A6

00 00

BSF EECON1, FREE

BSF EECON1, WR

NOP – hold PGC high for time P9 and low for time P10.

Step 4: Repeat Step 3, with the Address Pointer incremented by 64 until all rows are erased.

Done

Start

Hold PGC Low

for Time P10

All

rows

done?

Yes

Addr = 0

Configure

Device for

Row Erases

Addr = Addr + 64

Start Erase Sequence

and Hold PGC High

for Time P9

PIC18F2XXX/4XXX FAMILY

DS30009622M-page 24  2010-2015 Microchip Technology Inc.

3.2 Code Memory Programming

Programming code memory is accomplished by first loading data into the write buffer and then initiating a programming

sequence. The write and erase buffer sizes, shown in Table 3-4, can be mapped to any location of the same size,

beginning at 000000h. The actual memory write sequence takes the contents of this buffer and programs the proper

amount of code memory that contains the Table Pointer.

The programming duration is externally timed and is controlled by PGC. After a Start Programming command is issued

(4-bit command, ‘1111’), a NOP is issued, where the 4th PGC is held high for the duration of the programming time, P9.

After PGC is brought low, the programming sequence is terminated. PGC must be held low for the time specified by

Parameter P10 to allow high-voltage discharge of the memory array.

The code sequence to program a PIC18F2XXX/4XXX Family device is shown in Table 3-5. The flowchart, shown in

Figure 3-4, depicts the logic necessary to completely write a PIC18F2XXX/4XXX Family device. The timing diagram

that details the Start Programming command and Parameters P9 and P10 is shown in Figure 3-5.

Note: The TBLPTR register must point to the same region when initiating the programming sequence as it did

when the write buffers were loaded.

TABLE 3-4: WRITE AND ERASE BUFFER SIZES

Devices (Arranged by Family) Write Buffer Size (Bytes) Erase Buffer Size (Bytes)

PIC18F2221, PIC18F2321, PIC18F4221, PIC18F4321 8 64

PIC18F2450, PIC18F4450 16 64

PIC18F2410, PIC18F2510, PIC18F4410, PIC18F4510

32 64

PIC18F2420, PIC18F2520, PIC18F4420, PIC18F4520

PIC18F2423, PIC18F2523, PIC18F4423, PIC18F4523

PIC18F2480, PIC18F2580, PIC18F4480, PIC18F4580

PIC18F2455, PIC18F2550, PIC18F4455, PIC18F4550

PIC18F2458, PIC18F2553, PIC18F4458, PIC18F4553

PIC18F2515, PIC18F2610, PIC18F4515, PIC18F4610

64 64

PIC18F2525, PIC18F2620, PIC18F4525, PIC18F4620

PIC18F2585, PIC18F2680, PIC18F4585, PIC18F4680

PIC18F2682, PIC18F2685, PIC18F4682, PIC18F4685

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P39 P40-P42 P43-P45 P46-P48 P49-P51 P52-P54 P55-P56

PIC18F4510-E/ML

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