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ADSP-2186MBSTZ266R

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P43
REV. 0
ADSP-2186M
–13–
Data Memory
Data Memory (Full Memory Mode) is a 16-bit-wide space used
for the storage of data variables and for memory-mapped control
registers. The ADSP-2186M has 8K words on Data Memory
RAM on-chip. Part of this space is used by 32 memory-mapped
registers. Support also exists for up to two 8K external memory
overlay spaces through the external data bus. All internal accesses
ACCESSIBLE WHEN
DMOVLAY = 2
ACCESSIBLE WHEN
DMOVLAY = 1
0
x
0000 – 0
x
1FFF
1
0
x
0000 – 0
x
1FFF
1
EXTERNAL
MEMORY
32 MEMORY
MAPPED
REGISTERS
0
x
3FFF
INTERNAL
8160 WORDS
0
x
0000
DATA MEMORY
ADDR
0
x
3FE0
EXTERNAL 8K
DMOVLAY = 1, 2
0
x
1FFF
0
x
3FDF
0
x
2000
DM OVLAY = 0
RESERVED
0
x
0000 – 0
x
1FFF
DATA MEMORY
ALWAYS
ACCESSIBLE
AT ADDRESS
0
x2000 – 0x3FFF
NOTE:
1
SEE TABLE IV FOR DMOVLAY BITS
Figure 5. Data Memory Map
complete in one cycle. Accesses to external memory are timed
using the wait states specified by the DWAIT register and the
wait state mode bit.
Data Memory (Host Mode) allows access to all internal
memory. External overlay access is limited by a single external
address line (A0).
Table IV. DMOVLAY Bits
DMOVLAY Memory A13 A12:0
0 Reserved Not Applicable Not Applicable
1 External Overlay 1 0 13 LSBs of Address Between 0x2000 and 0x3FFF
2 External Overlay 2 1 13 LSBs of Address Between 0x2000 and 0x3FFF
Memory Mapped Registers (New to the ADSP-2186M)
The ADSP-2186M has three memory mapped registers that differ
from other ADSP-21xx Family DSPs. The slight modifications
to these registers (Wait State Control, Programmable Flag and
Composite Select Control, and System Control) provide the
ADSP-2186M’s wait state and BMS control features. Default
bit values at reset are shown; if no value is shown, the bit is unde-
fined at reset. Reserved bits are shown on a grey field. These bits
should always be written with zeros.
DWAIT IOWAIT3 IOWAIT2 IOWAIT1 IOWAIT0
DM(0x3FFE)
WAITSTATE CONTROL
1111111111111111
1514131211109876543210
WAIT STATE MODE SELECT
0 = NORMAL MODE (PWAIT, DWAIT, IOWAIT0–3 = N WAIT STATES, RANGING
FROM 0 TO 7)
1 = 2N + 1 MODE (PWAIT, DWAIT, IOWAIT0–3 = 2N + 1 WAIT STATES, RANGING
FROM 0 TO 15)
Figure 6. Wait State Control Register
BMWAIT CMSSEL
0 = DISABLE CMS
1 = ENABLE CMS
DM(0x3FE6)
PROGRAMMABLE FLAG AND COMPOSITE SELECT CONTROL
PFTYPE
0 = INPUT
1 = OUTPUT
(
WHERE BIT: 11-IOM, 10-BM, 9-DM, 8-PM
)
1111101100000000
1514131211109876543210
Figure 7. Programmable Flag and Composite Control
Register
Figure 8. System Control Register
I/O Space (Full Memory Mode)
The ADSP-2186M supports an additional external memory
space called I/O space. This space is designed to support simple
connections to peripherals (such as data converters and external
registers) or to bus interface ASIC data registers. I/O space sup-
ports 2048 locations of 16-bit wide data. The lower eleven bits
of the external address bus are used; the upper three bits are
undefined. Two instructions were added to the core ADSP-2100
Family instruction set to read from and write to I/O memory
space. The I/O space also has four dedicated three-bit wait state
registers, IOWAIT0–3, which in combination with the wait state
mode bit, specify up to 15 wait states to be automatically gener-
ated for each of four regions. The wait states act on address
ranges as shown in Table V.
REV. 0
–14–
ADSP-2186M
Table V. Wait States
Address Range Wait State Register
0x000–0x1FF IOWAIT0 and Wait State Mode Select Bit
0x200–0x3FF IOWAIT1 and Wait State Mode Select Bit
0x400–0x5FF IOWAIT2 and Wait State Mode Select Bit
0x600–0x7FF IOWAIT3 and Wait State Mode Select Bit
Composite Memory Select (CMS)
The ADSP-2186M has a programmable memory select signal that
is useful for generating memory select signals for memories
mapped to more than one space. The CMS signal is gener-
ated to have the same timing as each of the individual memory
select signals (PMS, DMS, BMS, IOMS) but can combine their
functionality.
Each bit in the CMSSEL register, when set, causes the CMS
signal to be asserted when the selected memory select is
asserted. For example, to use a 32K word memory to act as both
program and data memory, set the PMS and DMS bits in the
CMSSEL register and use the CMS pin to drive the chip
select of the memory, and use either DMS or PMS as the
additional address bit.
The CMS pin functions like the other memory select signals
with the same timing and bus request logic. A 1 in the enable bit
causes the assertion of the CMS signal at the same time as the
selected memory select signal. All enable bits default to 1 at reset,
except the BMS bit.
Byte Memory Select (BMS)
The ADSP-2186M’s BMS disable feature combined with the
CMS pin allows use of multiple memories in the byte memory
space. For example, an EPROM could be attached to the BMS
select, and an SRAM could be connected to CMS. Because at
reset BMS is enabled, the EPROM would be used for booting.
After booting, software could disable BMS and set the CMS
signal to respond to BMS, enabling the SRAM.
Byte Memory
The byte memory space is a bidirectional, 8-bit-wide, external
memory space used to store programs and data. Byte memory is
accessed using the BDMA feature. The byte memory space con-
sists of 256 pages, each of which is 16K × 8.
The byte memory space on the ADSP-2186M supports read and
write operations as well as four different data formats. The byte
memory uses data bits 15:8 for data. The byte memory uses data
bits 23:16 and address bits 13:0 to create a 22-bit address. This
allows up to a 4 meg × 8 (32 megabit) ROM or RAM to be used
without glue logic. All byte memory accesses are timed by the
BMWAIT register and the wait state mode bit.
Byte Memory DMA (BDMA, Full Memory Mode)
The byte memory DMA controller allows loading and storing of
program instructions and data using the byte memory space. The
BDMA circuit is able to access the byte memory space while the
processor is operating normally and steals only one DSP cycle
per 8-, 16- or 24-bit word transferred.
BDMA CONTROL
BMPAGE
BTYPE
BDIR
0 = LOAD FROM BM
1 = STORE TO BM
BCR
0 = RUN DURING BDMA
1 = HALT DURING BDMA
0000000000001000
1514131211109876543210
DM (0x3FE3)
BDMA
OVERLAY
BITS*
THESE BITS SHOULD ALWAYS
BE WRITTEN WITH ZEROS.
*
Figure 9. BDMA Control Register
The BDMA circuit supports four different data formats that are
selected by the BTYPE register field. The appropriate number
of 8-bit accesses are done from the byte memory space to build
the word size selected. Table VI shows the data formats sup-
ported by the BDMA circuit.
Table VI. Data Formats
BTYPE Internal Memory Space Word Size Alignment
00 Program Memory 24 Full Word
01 Data Memory 16 Full Word
10 Data Memory 8 MSBs
11 Data Memory 8 LSBs
Unused bits in the 8-bit data memory formats are filled with 0s.
The BIAD register field is used to specify the starting address
for the on-chip memory involved with the transfer. The 14-bit
BEAD register specifies the starting address for the external byte
memory space. The 8-bit BMPAGE register specifies the start-
ing page for the external byte memory space. The BDIR register
field selects the direction of the transfer. Finally, the 14-bit
BWCOUNT register specifies the number of DSP words to
transfer and initiates the BDMA circuit transfers.
BDMA accesses can cross page boundaries during sequential
addressing. A BDMA interrupt is generated on the completion
of the number of transfers specified by the BWCOUNT register.
The BWCOUNT register is updated after each transfer so it can
be used to check the status of the transfers. When it reaches zero,
the transfers have finished and a BDMA interrupt is generated.
The BMPAGE and BEAD registers must not be accessed by the
DSP during BDMA operations.
The source or destination of a BDMA transfer will always be
on-chip program or data memory.
When the BWCOUNT register is written with a nonzero value
the BDMA circuit starts executing byte memory accesses with wait
states set by BMWAIT. These accesses continue until the count
reaches zero. When enough accesses have occurred to create a
destination word, it is transferred to or from on-chip memory.
The transfer takes one DSP cycle. DSP accesses to external
memory have priority over BDMA byte memory accesses.
The BDMA Context Reset bit (BCR) controls whether the
processor is held off while the BDMA accesses are occurring.
Setting the BCR bit to 0 allows the processor to continue opera-
tions. Setting the BCR bit to 1 causes the processor to stop
execution while the BDMA accesses are occurring, to clear the
context of the processor, and start execution at address 0 when
the BDMA accesses have completed.
REV. 0
ADSP-2186M
–15–
The BDMA overlay bits specify the OVLAY memory blocks to
be accessed for internal memory. For ADSP-2186M, set to zero
BDMA overlay bits in BDMA control register.
The BMWAIT field, which has four bits on ADSP-2186M,
allows selection of up to 15 wait states for BDMA transfers.
Internal Memory DMA Port (IDMA Port; Host Memory
Mode)
The IDMA Port provides an efficient means of communication
between a host system and the ADSP-2186M. The port is used
to access the on-chip program memory and data memory of the
DSP with only one DSP cycle per word overhead. The IDMA
port cannot, however, be used to write to the DSP’s memory-
mapped control registers. A typical IDMA transfer process is
described as follows:
1. Host starts IDMA transfer.
2. Host checks IACK control line to see if the DSP is busy.
3. Host uses IS and IAL control lines to latch either the DMA
starting address (IDMAA) or the PM/DM OVLAY selection
into the DSP’s IDMA control registers. If Bit 15 = 1, the
value of bits 7:0 represent the IDMA overlay: bits 14:8 must
be set to 0. If Bit 15 = 0, the value of Bits 13:0 represent the
starting address of internal memory to be accessed and
Bit 14 reflects PM or DM for access. For ADSP-2186M,
IDDMOVLAY and IDPMOVLAY bits in IDMA overlay
register should be set to zero.
4. Host uses IS and IRD (or IWR) to read (or write) DSP inter-
nal memory (PM or DM).
5. Host checks IACK line to see if the DSP has completed the
previous IDMA operation.
6. Host ends IDMA transfer.
The IDMA port has a 16-bit multiplexed address and data bus
and supports 24-bit program memory. The IDMA port is com-
pletely asynchronous and can be written while the ADSP-2186M
is operating at full speed.
The DSP memory address is latched and then automatically incre-
mented after each IDMA transaction. An external device can
therefore access a block of sequentially addressed memory by
specifying only the starting address of the block. This increases
throughput as the address does not have to be sent for each
memory access.
IDMA Port access occurs in two phases. The first is the IDMA
Address Latch cycle. When the acknowledge is asserted, a 14-bit
address and 1-bit destination type can be driven onto the bus by
an external device. The address specifies an on-chip memory
location, the destination type specifies whether it is a DM or
PM access. The falling edge of the IDMA address latch signal
(IAL) or the missing edge of the IDMA select signal (IS) latches
this value into the IDMAA register.
Once the address is stored, data can be read from, or written to,
the ADSP-2186M’s on-chip memory. Asserting the select line
(IS) and the appropriate read or write line (IRD and IWR
respectively) signals the ADSP-2186M that a particular transac-
tion is required. In either case, there is a one-processor-cycle
delay for synchronization. The memory access consumes one
additional processor cycle.
Once an access has occurred, the latched address is automati-
cally incremented, and another access can occur.
Through the IDMAA register, the DSP can also specify the
starting address and data format for DMA operation. Asserting
the IDMA port select (IS) and address latch enable (IAL) directs
the ADSP-2186M to write the address onto the IAD0–14 bus
into the IDMA Control Register. If Bit 15 is set to 0, IDMA
latches the address. If Bit 15 is set to 1, IDMA latches into the
OVLAY register. This register, shown below, is memory mapped
at address DM (0x3FE0). Note that the latched address (IDMAA)
cannot be read back by the host. When Bit 14 in 0x3FE7 is set
to 1, timing in Figure 31 applies for short reads. When Bit 14
in 0x3FE7 is set to zero, short reads use the timing shown in Fig-
ure 32. For ADSP-2186M, IDDMOVLAY and IDPMOVLAY
bits in IDMA overlay register should be set to zero.
Refer to the following figures for more information on IDMA
and DMA memory maps.
IDMA OVERLAY
DM (0x3FE7)
RESERVED SET TO 0
1,2
IDDMOVLAY
2
IDPMOVLAY
2
000000000000000
1514131211109876543210
SHORT READ ONLY
0 = ENABLE
1 = DISABLE
IDMA CONTROL (U = UNDEFINED AT RESET)
DM (0x3FE0)
IDMAA ADDRESS
UUUUUUUUUUUUUUU
1514131211109876543210
IDMAD DESTINATION MEMORY TYPE
0 = PM
1 = DM
NOTES:
1
RESERVED BITS ARE SHOWN ON A GRAY FIELD.
2
THESE BITS SHOULD ALWAYS BE WRITTEN WITH ZEROS.
0
RESERVED SET TO 0
0
RESERVED SET TO 0
Figure 10. IDMA Control/OVLAY Registers
RESERVED
0
x
2000 –
0
x
3FFF
DMA
PROGRAM MEMORY
ALWAYS
ACCESSIBLE
AT ADDRESS
0
x
0000 – 0
x
1FFF
0
x
0000 –
0
x
1FFF
DMA
DATA MEMORY
ALWAYS
ACCESSIBLE
AT ADDRESS
0
x
2000 – 0
x
3FFF
NOTE: IDMA AND BDMA HAVE SEPARATE DMA CONTROL REGISTERS.
RESERVED
Figure 11. Direct Memory Access—PM and DM
Memory Maps
Bootstrap Loading (Booting)
The ADSP-2186M has two mechanisms to allow automatic load-
ing of the internal program memory after reset. The method for
booting is controlled by the Mode A, B, and C configuration bits.
When the MODE pins specify BDMA booting, the ADSP-2186M
initiates a BDMA boot sequence when reset is released.
The BDMA interface is set up during reset to the following
defaults when BDMA booting is specified: the BDIR, BMPAGE,
BIAD, and BEAD registers are set to 0, the BTYPE register is
set to 0 to specify program memory 24-bit words, and the
BWCOUNT register is set to 32. This causes 32 words of
on-chip program memory to be loaded from byte memory.
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ADSP-2186MBSTZ266R

Mfr. #:
Buy ADSP-2186MBSTZ266R
Manufacturer:
Analog Devices Inc.
Description:
Digital Signal Processors & Controllers - DSP, DSC 16B 75 MIPS 2.5V 2 Serial Prts Host Prt
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