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ADSP-2186MBSTZ266R

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P43
SOFTWARE AND SYSTEMS REQUIREMENTS
• Software and Tools Anomalies Search
TOOLS AND SIMULATIONS
• ADSP-218xM IBIS Datafile (LQFP Package)
DESIGN RESOURCES
• ADSP-2186M Material Declaration
• PCN-PDN Information
• Quality And Reliability
• Symbols and Footprints
DISCUSSIONS
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SAMPLE AND BUY
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TECHNICAL SUPPORT
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REV. 0
–2–
ADSP-2186M
TABLE OF CONTENTS
FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
FUNCTIONAL BLOCK DIAGRAM . . . . . . . . . . . . . . . . 1
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . 3
DEVELOPMENT SYSTEM . . . . . . . . . . . . . . . . . . . . . . . 3
Additional Information . . . . . . . . . . . . . . . . . . . . . . . . . . 3
ARCHITECTURE OVERVIEW . . . . . . . . . . . . . . . . . . . . 4
Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
PIN DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Common-Mode Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Memory Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Full Memory Mode Pins (Mode C = 0) . . . . . . . . . . . . . . 7
Host Mode Pins (Mode C = 1) . . . . . . . . . . . . . . . . . . . . 7
Terminating Unused Pins . . . . . . . . . . . . . . . . . . . . . . . . 8
Pin Terminations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
LOW POWER OPERATION . . . . . . . . . . . . . . . . . . . . . . . 9
Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Idle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Slow Idle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
SYSTEM INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
MODES OF OPERATION . . . . . . . . . . . . . . . . . . . . . . . 11
Setting Memory Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Passive Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Active Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
IACK Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
MEMORY ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . 12
Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Memory Mapped Registers (New to the
ADSP-2186M) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
I/O Space (Full Memory Mode) . . . . . . . . . . . . . . . . . . . 13
Composite Memory Select (CMS) . . . . . . . . . . . . . . . . . 14
Byte Memory Select (BMS) . . . . . . . . . . . . . . . . . . . . . . 14
Byte Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Byte Memory DMA (BDMA, Full Memory Mode) . . . . 14
Internal Memory DMA Port
(IDMA Port; Host Memory Mode) . . . . . . . . . . . . . . 15
Bootstrap Loading (Booting) . . . . . . . . . . . . . . . . . . . . . 15
IDMA Port Booting . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Bus Request and Bus Grant . . . . . . . . . . . . . . . . . . . . . . 16
Flag I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Instruction Set Description . . . . . . . . . . . . . . . . . . . . . . 16
DESIGNING AN EZ-ICE-COMPATIBLE SYSTEM . . . 16
Target Board Connector for EZ-ICE Probe . . . . . . . . . . 17
Target Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . 17
PM, DM, BM, IOM, AND CM . . . . . . . . . . . . . . . . . . . . 17
Target System Interface Signals . . . . . . . . . . . . . . . . . . . 17
RECOMMENDED OPERATING CONDITIONS . . . . . 18
ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . 18
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . 19
TIMING SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . 19
GENERAL NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
TIMING NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
MEMORY TIMING SPECIFICATIONS . . . . . . . . . . . . 19
FREQUENCY DEPENDENCY FOR
TIMING SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . 20
ENVIRONMENTAL CONDITIONS . . . . . . . . . . . . . . . 20
POWER DISSIPATION . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Output Drive Currents . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Capacitive Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
TEST CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Output Disable Time . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Output Enable Time . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Clock Signals and Reset . . . . . . . . . . . . . . . . . . . . . . . . . 23
Interrupts and Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Bus Request–Bus Grant . . . . . . . . . . . . . . . . . . . . . . . . . 25
Memory Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Memory Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
IDMA Address Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
IDMA Write, Short Write Cycle . . . . . . . . . . . . . . . . . . 30
IDMA Write, Long Write Cycle . . . . . . . . . . . . . . . . . . . 31
IDMA Read, Long Read Cycle . . . . . . . . . . . . . . . . . . . 32
IDMA Read, Short Read Cycle . . . . . . . . . . . . . . . . . . . 33
IDMA Read, Short Read Cycle in Short Read
Only Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
100-LEAD LQFP PIN CONFIGURATION . . . . . . . . . . 35
LQFP Package Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
144-Ball Mini-BGA Package Pinout . . . . . . . . . . . . . . . . . 37
Mini-BGA Package Pinout . . . . . . . . . . . . . . . . . . . . . . . . 38
OUTLINE DIMENSIONS
100-Lead Metric Thin Plastic Quad Flatpack
(LQFP) (ST-100) . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
OUTLINE DIMENSIONS
144-Ball Mini-BGA (CA-144) . . . . . . . . . . . . . . . . . . . . 40
ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Tables
Table I. Interrupt Priority and Interrupt
Vector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table II. Modes of Operation . . . . . . . . . . . . . . . . . . . . . . 11
Table III. PMOVLAY Bits . . . . . . . . . . . . . . . . . . . . . . . . 12
Table IV. DMOVLAY Bits . . . . . . . . . . . . . . . . . . . . . . . . 13
Table V. Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table VI. Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . . 14
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ADSP-2186M
–3–
GENERAL DESCRIPTION
The ADSP-2186M is a single-chip microcomputer optimized
for digital signal processing (DSP) and other high-speed numeric
processing applications.
The ADSP-2186M combines the ADSP-2100 family base archi-
tecture (three computational units, data address generators, and
a program sequencer) with two serial ports, a 16-bit internal DMA
port, a byte DMA port, a programmable timer, Flag I/O, exten-
sive interrupt capabilities, and on-chip program and data memory.
The ADSP-2186M integrates 40K bytes of on-chip memory
configured as 8K words (24-bit) of program RAM, and 8K
words (16-bit) of data RAM. Power-down circuitry is also pro-
vided to meet the low power needs of battery-operated portable
equipment. The ADSP-2186M is available in a 100-lead LQFP
package and 144 Ball Mini-BGA.
In addition, the ADSP-2186M supports new instructions, which
include bit manipulations—bit set, bit clear, bit toggle, bit test—
new ALU constants, new multiplication instruction (× squared),
biased rounding, result-free ALU operations, I/O memory trans-
fers, and global interrupt masking, for increased flexibility.
Fabricated in a high-speed, low-power, CMOS process, the
ADSP-2186M operates with a 13.3 ns instruction cycle time.
Every instruction can execute in a single processor cycle.
The ADSP-2186M’s flexible architecture and comprehensive
instruction set allow the processor to perform multiple opera-
tions in parallel. In one processor cycle, the ADSP-2186M can:
• Generate the next program address
• Fetch the next instruction
• Perform one or two data moves
• Update one or two data address pointers
• Perform a computational operation
This takes place while the processor continues to:
• Receive and transmit data through the two serial ports
• Receive and/or transmit data through the internal DMA port
• Receive and/or transmit data through the byte DMA port
• Decrement timer
DEVELOPMENT SYSTEM
The ADSP-2100 Family Development Software, a complete set
of tools for software and hardware system development, supports
the ADSP-2186M. The System Builder provides a high-level
method for defining the architecture of systems under develop-
ment. The Assembler has an algebraic syntax that is easy to
program and debug. The Linker combines object files into an
executable file. The Simulator provides an interactive instruction-
level simulation with a reconfigurable user interface to display
different portions of the hardware environment.
The EZ-KIT Lite is a hardware/software kit offering a complete
evaluation environment for the ADSP-218x family: an ADSP-
2189M-based evaluation board with PC monitor software plus
assembler, linker, simulator, and PROM splitter software. The
ADSP-2189M EZ-KIT Lite is a low cost, easy to use hardware
platform on which you can quickly get started with your DSP
software design. The EZ-KIT Lite includes the following features:
• 75 MHz ADSP-2189M
• Full 16-Bit Stereo Audio I/O with AD73322 Codec
• RS-232 Interface
• EZ-ICE Connector for Emulator Control
• DSP Demo Programs
• Evaluation Suite of VisualDSP
The ADSP-218x EZ-ICE
®
Emulator aids in the hardware
debugging of an ADSP-2186M system. The ADSP-2186M
integrates on-chip emulation support with a 14-pin ICE-Port
interface. This interface provides a simpler target board connec-
tion that requires fewer mechanical clearance considerations
than other ADSP-2100 Family EZ-ICEs. The ADSP-2186M
device need not be removed from the target system when using
the EZ-ICE, nor are any adapters needed. Due to the small
footprint of the EZ-ICE connector, emulation can be supported
in final board designs.
The EZ-ICE performs a full range of functions, including:
• In-target operation
• Up to 20 breakpoints
• Single-step or full-speed operation
• Registers and memory values can be examined and altered
• PC upload and download functions
• Instruction-level emulation of program booting and execution
• Complete assembly and disassembly of instructions
• C source-level debugging
See Designing An EZ-ICE-Compatible Target System in the
ADSP-2100 Family EZ-Tools Manual (ADSP-2181 sections) as
well as the Designing an EZ-ICE-Compatible System section of
this data sheet for the exact specifications of the EZ-ICE target
board connector.
Additional Information
This data sheet provides a general overview of ADSP-2186M
functionality. For additional information on the architecture and
instruction set of the processor, refer to the ADSP-2100 Family
User’s Manual. For more information about the development
tools, refer to the ADSP-2100 Family Development Tools
data sheet.
EZ-ICE is a registered trademark of Analog Devices, Inc.
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ADSP-2186MBSTZ266R

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Analog Devices Inc.
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Digital Signal Processors & Controllers - DSP, DSC 16B 75 MIPS 2.5V 2 Serial Prts Host Prt
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