REV. 0
ADSP-2186M
–25–
Parameter Min Max Unit
Bus Request–Bus Grant
Timing Requirements:
t
BH
BR Hold after CLKOUT High
1
0.25t
CK
+ 2 ns
t
BS
BR Setup before CLKOUT Low
1
0.25t
CK
+ 10 ns
Switching Characteristics:
t
SD
CLKOUT High to xMS, RD, WR Disable 0.25t
CK
+ 8 ns
t
SDB
xMS, RD, WR Disable to BG Low 0 ns
t
SE
BG High to xMS, RD, WR Enable 0 ns
t
SEC
xMS, RD, WR Enable to CLKOUT High 0.25t
CK
– 3ns
t
SDBH
xMS, RD, WR Disable to BGH Low
2
0ns
t
SEH
BGH High to xMS, RD, WR Enable
2
0ns
NOTES
xMS = PMS, DMS, CMS, IOMS, BMS.
1
BR is an asynchronous signal. If BR meets the setup/hold requirements, it will be recognized during the current clock cycle; otherwise the signal will be recognized on
the following cycle. Refer to the ADSP-2100 Family User’s Manual for BR/BG cycle relationships.
2
BGH is asserted when the bus is granted and the processor or BDMA requires control of the bus to continue.
CLKOUT
t
SD
t
SDB
t
SE
t
SEC
t
SDBH
t
SEH
t
BS
BR
t
BH
CLKOUT
PMS, DMS
BMS, RD
WR
BG
BGH
Figure 23. Bus Request–Bus Grant
