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PCA2125TS/1,112

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36
PCA2125_1 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 01 — 28 July 2008 13 of 36
NXP Semiconductors
PCA2125
SPI Real-time clock/calendar
To prevent the timer flags being overwritten while clearing bit AF, a logic AND is performed
during a write access. The flag is reset by writing a logic 0 but its value is not affected by
writing a logic 1.
Table 23 shows what instruction must be sent to clear bit AF. In this example, bit MSF and
bit TF are unaffected.
8.6 Timer functions
The countdown timer has four selectable source clocks allowing for countdown periods in
the range from less than 1 ms to more than 4 hours. There are also two pre-defined timers
which can be used to generate an interrupt once per second or once per minute.
Registers Control_2 (01h), Timer_control (0Eh) and Countdown_timer (0Fh) are used to
control the timer function and output.
8.6.1 Second and minute interrupt
The second and minute interrupts (bits SI and MI) are pre-defined timers for generating
periodic interrupts. The timers can be enabled independently of one another, however a
minute interrupt enabled on top of a second interrupt will not be distinguishable since it will
occur at the same time; see Figure 9.
Table 22. Flag location in register Control_2
Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Control_2 - - MSF - AF TF - -
Table 23. Example to clear only AF (bit 3) in register Control_2
Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Control_2 - - 1 - 0 1 - -
Table 24. Register Timer_control (address 0Eh) bit description
Bit Symbol Value Description Reference
7 TE 0 countdown timer is disabled
Section 8.6.2
1 countdown timer is enabled
6 to 2 - 0 unused
1 to 0 CTD[1:0] 00 4096 Hz countdown timer source clock
01 64 Hz countdown timer source clock
10 1 Hz countdown timer source clock
11
1
⁄
60
Hz countdown timer source clock
Table 25. Register Countdown_timer (address 0Fh) bit description
Bit Symbol Value Description Reference
7 to 0 COUNTDOWN_TIMER[7:0] 00h to FFh countdown value = n.
Section 8.6.2
CountdownPeriod
n
SourceClockFrequency
---------------------------------------------------------------
=
PCA2125_1 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 01 — 28 July 2008 14 of 36
NXP Semiconductors
PCA2125
SPI Real-time clock/calendar
The minute and second flag (bit MSF) is set to logic 1 when either the seconds or the
minutes counter increments according to the currently enabled interrupt. The flag can be
read and cleared by the interface. The status of bit MSF does not affect the INT pulse
generation. If the MSF flag is not cleared prior to the next coming interrupt period, an INT
pulse will still be generated.
The purpose of the flag is to allow the controlling system to interrogate the PCA2125 and
identify the source of the interrupt such as the minute/second or countdown timer.
a. INT and MSF when SI enabled (MSF flag not cleared after an interrupt)
b.
INT and MSF when only MI enabled
Bit TI_TP is set to logic 1 resulting in
1
⁄
64
Hz wide interrupt pulse.
Fig 9. INT example for bits SI and MI
Table 26. Effect of bits MI and SI on
INT generation
Minute interrupt (bit MI) Second interrupt (bit SI) Result
0 0 no interrupt generated
1 0 an interrupt once per minute
0 1 an interrupt once per second
1 1 an interrupt once per second
001aai520
seconds counter
minutes counter
INT
MSF
58
59 0059 00
11 12
01
001aai521
seconds counter
minutes counter
INT
MSF
58
59 0059 00
11 12
01
PCA2125_1 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 01 — 28 July 2008 15 of 36
NXP Semiconductors
PCA2125
SPI Real-time clock/calendar
[1] In the case of bit MI = 1 and bit SI = 0, bit MSF will be cleared automatically after 1 second.
8.6.2 Countdown timer function
The 8-bit countdown timer at address 0Fh is controlled by the timer control register at
address 0Eh. The timer control register determines one of 4 source clock frequencies for
the timer (4096 Hz, 64 Hz, 1 Hz, or
1
⁄
60
Hz), and enables or disables the timer.
[1] When not in use, bits CTD[1:0] must be set to
1
⁄
60
Hz for power saving.
Remark: Note that all timings which are generated from the 32.768 kHz oscillator are
based on the assumption that there is 0 ppm deviation. Deviation in oscillator frequency
will result in a corresponding deviation in timings. This is not applicable to interface timing.
The timer counts down from a software-loaded 8-bit binary value n. Loading the counter
with 0 effectively stops the timer. Values from 1 to 255 are valid. When the counter
reaches 1, the countdown timer flag (bit TF) will be set and the counter automatically
re-loads and starts the next timer period. Reading the timer will return the current value of
the countdown counter; see Figure 10.
Table 27. Effect of bits MI and SI on bit MSF
Minute interrupt (bit MI) Second interrupt (bit SI) Result
0 0 MSF never set
1 0 MSF set when minutes counter
increments
[1]
0 1 MSF set when seconds counter
increments
1 1 MSF set when seconds counter
increments
Table 28. Bits CTD1 and CTD0 for timer frequency selection and countdown timer
durations
Bits CTD[1:0] Timer source clock
frequency
Delay
Minimum timer duration
n= 1
Maximum timer duration
n = 255
00 4096 Hz 244 µs 62.256 ms
01 64 Hz 15.625 ms 3.984 s
10 1 Hz 1 s 255 s
11
1
⁄
60
Hz 60 s
[1]
4 h 15 min
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PCA2125TS/1,112

Mfr. #:
Buy PCA2125TS/1,112
Manufacturer:
NXP Semiconductors
Description:
IC RTC CLK/CALENDAR SPI 14-TSSOP
Lifecycle:
New from this manufacturer.
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