PCA2125_1 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 01 — 28 July 2008 24 of 36
NXP Semiconductors
PCA2125
SPI Real-time clock/calendar
8.11 3-line SPI
Data transfer to and from the device is made via a 3-wire SPI-bus; see Table 37. The data
lines for input and output are split. The data input and output lines can be connected
together to facilitate a bidirectional data bus. The chip enable signal is used to identify the
transmitted data. Each data transfer is a byte, with the Most Significant Bit (MSB) sent
first; see Figure 18.
The transmission is controlled by the active HIGH chip enable signal CE. The first byte
transmitted is the command byte. Subsequent bytes will be either data to be written or
data to be read. Data is captured on the rising edge of the clock and transferred internally
on the falling edge.
The command byte defines the address of the first register to be accessed and the
read/write mode. The address counter will auto increment after every access and will
reset to zero after the last valid register is accessed. The read/write bit (R/W) defines if the
following bytes will be read or write information.
In Figure 19 the Seconds register is set to 45 seconds and the Minutes register to
10 minutes.
Table 37. Serial interface
Pin Function Description
CE chip enable input when LOW, the interface is reset; pull-down resistor included; active
input can be higher than V
DD
, but must not be wired HIGH
permanently
SCL serial clock input when pin CE = LOW, this input might float; input can be higher than
V
DD
SDI serial data input when pin CE = LOW, this input might float; input can be higher than
V
DD
; input data is sampled on the rising edge of SCL
SDO serial data output push-pull output; drives from V
SS
to V
DD
; output data is changed on
the falling edge of SCL
Fig 18. Data transfer overview
Table 38. Command byte definition
Bit Symbol Value Description
7R/
W data read or data write selection
0 write data
1 read data
6 to 4 SA 001 subaddress; other codes will cause the device to ignore data
transfer
3 to 0 RA 00h to 0Fh register address range
001aaf914
COMMANDdata bus
chip enable
DATA DATADATA
