PCA2125_1 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 01 — 28 July 2008 28 of 36
NXP Semiconductors
PCA2125
SPI Real-time clock/calendar
[1] For reliable oscillator start at power-up: V
DD
=V
DD(min)
+ 0.3 V.
[2] Timer source clock =
1
⁄
60
Hz; voltage on pins CE, SDI and SCL at V
DD
or V
SS
.
[3] Implicit by design.
12. Dynamic characteristics
[1] Bus will be held up by bus capacitance; use RC time constant with application values.
I
OH
HIGH-level output current pin SDO; V
OH
= 4.6 V; V
DD
= 5 V - - 1.5 mA
I
OL
LOW-level output current pins INT, SDO and CLKOUT;
V
OL
= 0.4 V; V
DD
=5V
−1.5 - - mA
I
OL
LOW-level output current pin OSCO; V
OL
= 0.4 V; V
DD
=5V −1--mA
I
LO
output leakage current V
O
=V
DD
or V
SS
−10 +1µA
C
ext
external capacitance - 25 - pF
Table 40. Static characteristics
…continued
V
DD
= 1.3 V to 5.5 V; V
SS
=0V; T
amb
=
−
40
°
C to +125
°
C; f
osc
= 32.768 kHz; quartz R
s
=60k
Ω
; C
L
= 12.5 pF; unless
otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
Table 41. Dynamic characteristics
V
DD
= 1.6 V to 5.5 V; V
SS
=0V; T
amb
=
−
40
°
C to +125
°
C.
All timing values are valid within the operating supply voltage at ambient temperature and referenced to V
IL
and V
IH
with an
input voltage swing of V
SS
to V
DD
.
Symbol Parameter Conditions V
DD
= 1.6 V V
DD
= 2.7 V V
DD
= 4.5 V V
DD
= 5.5 V Unit
Min Max Min Max Min Max Min Max
Pin SCL
f
clk(SCL)
SCL clock frequency - 1.5 - 4.76 - 5.00 - 6.25 MHz
t
SCL
SCL time 660 - 210 - 200 - 160 - ns
t
clk(H)
clock HIGH time 320 - 100 - 100 - 70 - ns
t
clk(L)
clock LOW time 320 - 110 - 100 - 90 - ns
t
r
rise time - 100 - 100 - 100 - 100 ns
t
f
fall time - 100 - 100 - 100 - 100 ns
Pin CE
t
su(CE)
CE set-up time 30 - 30 - 30 - 30 - ns
t
h(CE)
CE hold time 100 - 60 - 40 - 30 - ns
t
rec(CE)
CE recovery time 100 - 100 - 100 - 100 - ns
t
w(CE)
CE pulse width - 0.99 - 0.99 - 0.99 - 0.99 s
Pin SDI
t
su
set-up time 25 - 15 - 15 - 10 - ns
t
h
hold time 100 - 60 - 40 - 30 - ns
Pin SDO
t
d(R)SDO
SDO read delay time bus load = 85 pF - 320 - 110 - 100 - 90 ns
t
dis(SDO)
SDO disable time no load value
[1]
- 50 - 30 - 30 - 25 ns
t
t(SDI-SDO)
transition time from
SDI to SDO
to avoid bus conflict 0 - 0 - 0 - 0 - ns
