PCA2125_1 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 01 — 28 July 2008 7 of 36
NXP Semiconductors
PCA2125
SPI Real-time clock/calendar
8.3 Control registers
Table 6. Control_1 register (address 00h) bit description
Bit Symbol Value Description Reference
7 EXT_TEST 0 normal mode
Section 8.9
1 external clock test mode
6 - 0 unused
5 STOP 0 RTC source clock runs
Section 8.10
1 RTC divider chain flip-flops are asynchronously set
to logic 0; the RTC clock is stopped (CLKOUT at
32.768 kHz, 16.384 kHz or 8.192 kHz is still
available)
4 - 0 unused -
3 POR_OVRD 0 power-on reset override facility is disabled; set to
logic 0 for normal operation
Section 8.2.1
1 power-on reset override is enabled
2 12_24 0 24 hour mode is selected
Table 11
1 12 hour mode is selected
1 to 0 - 0 unused -
Table 7. Control_2 register (address 01h) bit description
Bit Symbol Value Description Reference
7 MI 0 minute interrupt is disabled
Section 8.6.1
1 minute interrupt is enabled
6 SI 0 second interrupt is disabled
1 second interrupt is enabled
5 MSF 0 no minute or second interrupt generated
Section 8.6
1 flag set when minute or second interrupt generated;
flag must be cleared to clear interrupt
4 TI_TP 0 interrupt pin follows timer flags
Section 8.7.2
1 interrupt pin generates a pulse
3 AF 0 no alarm interrupt generated
Section 8.5.1
1 flag set when alarm triggered; flag must be cleared
to clear interrupt
2 TF 0 no countdown timer interrupt generated -
1 flag set when countdown timer interrupt generated;
flag must be cleared to clear interrupt
-
1 AIE 0 no interrupt generated from the alarm flag
Section 8.7.3
1 interrupt generated when alarm flag set
0 TIE 0 no interrupt generated from the countdown timer
flag
Section 8.7
1 interrupt generated when countdown timer flag set