PCA2125_1 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 01 — 28 July 2008 17 of 36
NXP Semiconductors
PCA2125
SPI Real-time clock/calendar
When reading the timer, the current countdown value is returned and not the initial
value n. For accurate read back of the countdown value, the SPI-bus clock (SCL) must be
operating at a frequency of at least twice the selected timer clock. Since it is not possible
to freeze the countdown timer counter during read back, it is recommended to read the
register twice and check for consistent results.
8.6.3 Timer flags
When a minute or second interrupt occurs, bit MSF is set to logic 1. Similarly, at the end of
a timer countdown, bit TF is set to logic 1. These bits maintain their value until overwritten
by software. If both countdown timer and minute/second interrupts are required in the
application, the source of the interrupt can be determined by reading these bits. To
prevent one flag being overwritten while clearing another, a logic AND is performed during
a write access. The flag is reset by writing a logic 0 but its value is not affected by writing a
logic 1.
Three examples are given for clearing the flags. Flags MSF and TF are cleared by a write
command, therefore bits 7, 6, 4, 1 and 0 must be written with their previous values.
Repeatedly re-writing these bits has no influence on the functional behavior.
Table 31, Table 32 and Table 33 show what instruction must be sent to clear the
appropriate flag.
Clearing the alarm flag (bit AF) operates in exactly the same way; see Section 8.5.1.
8.7 Interrupt output
An active LOW interrupt signal is available at pin INT. Operation is controlled via the bits
of control register 2. Interrupts can be sourced from three places: second/minute timer,
countdown timer and alarm function.
Bit TI_TP configures the timer generated interrupts to be either a pulse or to follow the
status of the interrupt flags (bits TF and MSF).
Table 30. Flag location in register Control_2
Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Control_2 - - MSF - AF TF - -
Table 31. Example to clear only TF (bit 2) in register Control_2
Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Control_2 - - 1 - 1 0 - -
Table 32. Example to clear only MSF (bit 5) in register Control_2
Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Control_2 - - 0 - 1 1 - -
Table 33. Example to clear both TF and MSF (bits 2 and 5) in register Control_2
Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Control_2 - - 0 - 1 0 - -
