PCA2125_1 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 01 — 28 July 2008 4 of 36
NXP Semiconductors
PCA2125
SPI Real-time clock/calendar
The first two registers at addresses 00h and 01h (Control_1 and Control_2) are used
as control registers.
Registers at addresses 02h to 08h (Seconds, Minutes, Hours, Days, Weekdays,
Months, Years) are used as counters for the clock function. Seconds, minutes, hours,
days, months and years are all coded in Binary Coded Decimal (BCD) format. When
one of the RTC registers is read the contents of all counters are frozen. Therefore,
faulty reading of the clock/calendar during a carry condition is prevented.
Registers at addresses 09h to 0Ch (Minute_alarm, Hour_alarm, Day_alarm,
Weekday_alarm) define the alarm condition.
Register at address 0Dh (CLKOUT_control) defines the clock out mode.
Registers at addresses 0Eh and 0Fh (Timer_control and Countdown_timer) are used
for the countdown timer function. The countdown timer has four selectable source
clocks allowing for countdown periods in the range from less than 1 ms to more than 4
hours. There are also two pre-defined timers which can be used to generate an
interrupt once per second or once per minute. These are defined in register Control_2
(01h).
8.1 Register overview
The time registers are encoded in BCD to simplify application use. Other registers are
either bit-wise or standard binary.
[1] Ten’s place.
Table 4. Register overview
Bits labeled ‘-’ are not implemented and will return a logic 0 when read. Bit positions labeled ‘0’ should always be written with
logic 0.
Address Register name Bit
7 6 5 4 3 2 1 0
00h Control_1 EXT_TEST 0 STOP 0 POR_OVRD 12_24 0 0
01h Control_2 MI SI MSF TI_TP AF TF AIE TIE
02h Seconds RF SECONDS
[1]
SECONDS
03h Minutes - MINUTES
[1]
MINUTES
04h Hours - - AMPM HOURS
[1]
HOURS
- - HOURS
[2]
HOURS
05h Days - - DAYS
[1]
DAYS
06h Weekdays - - - - - WEEKDAYS
07h Months - - - MONTHS
[1]
MONTHS
08h Years YEARS
[1]
YEARS
09h Minute_alarm AEN_M MINUTE_ALARM
[1]
MINUTE_ALARM
0Ah Hour_alarm AEN_H - AMPM HOUR_ALARM
[1]
HOUR_ALARM
- HOUR_ALARM
[2]
HOUR_ALARM
0Bh Day_alarm AEN_D - DAY_ALARM
[1]
DAY_ALARM
0Ch Weekday_alarm AEN_W - - - - WEEKDAY_ALARM
0Dh CLKOUT_control - - - - - COF
0Eh Timer_control TE - - - - - CTD
0Fh Countdown_timer COUNTDOWN_TIMER
PCA2125_1 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 01 — 28 July 2008 5 of 36
NXP Semiconductors
PCA2125
SPI Real-time clock/calendar
[2] Ten’s place in 24 h mode.
8.2 Reset
The PCA2125 includes an internal reset circuit which is active whenever the oscillator is
stopped; see Figure 3. The oscillator can be stopped, for example, by connecting one of
the oscillator pins OSCI or OSCO to ground.
The oscillator is considered to be stopped during the time between power-up and stable
crystal resonance; see Figure 4. This time can be in the range 200 ms to 2 s depending
on crystal type, temperature and supply voltage. Whenever an internal reset occurs, the
reset flag bit RF is set.
Fig 3. Reset system
Fig 4. Power-on reset
Table 5. Register reset value
Bits labeled ‘-’ are not implemented and will return a ‘0’ when read. Bits labeled ‘X’ are undefined at
power-up and unchanged by subsequent resets.
Address Register name Bit
7 6 5 4 3 2 1 0
00h Control_1 0 0 0 - 1 0 - -
01h Control_2 00000000
02h Seconds 1 XXXXXXX
03h Minutes - XXXXXXX
04h Hours - - XXXXXX
05h Days - -XXXXXX
06h Weekdays -----XXX
001aaf898
SDI
CE
0 = override inactive
0 = clear override mode
0 = stopped, 1 = running
osc stopped
1 = override active
1 = override possible
CLEAR
POR
OVERRIDE
Bit
POR_OVRD
OSCILLATOR
reset
001aaf897
chip in reset
chip not in reset
t
V
DD
oscillation
internal
reset
PCA2125_1 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 01 — 28 July 2008 6 of 36
NXP Semiconductors
PCA2125
SPI Real-time clock/calendar
After reset, the following mode is entered:
32.768 kHz on pin CLKOUT active
Power-on reset override available to be set
24 hour mode is selected
The SPI-bus is initialized whenever the chip enable pin CE is inactive (LOW).
8.2.1 Power-on reset override
The Power-On Reset (POR) duration is directly related to the crystal oscillator start-up
time. Due to the long start-up times experienced by these types of circuits, a mechanism
has been built in to disable the POR and hence speed up the on-board test of the device.
The setting of this mode requires that bit POR_OVRD be set to logic 1 and that the signals
at the SPI-bus pins SDI and CE are toggled as illustrated in Figure 5. All timings are
required minimums.
Once the override mode has been entered, the device immediately stops being reset and
set-up operation can commence i.e. entry into the external clock test mode via the
SPI-bus access. The override mode can be cleared by writing a logic 0 to bit POR_OVRD.
Bit POR_OVRD must be set to logic 1 before a re-entry into the override mode is possible.
Setting bit POR_OVRD to logic 0 during normal operation has no effect except to prevent
accidental entry into the POR override mode. This is the recommended setting.
07h Months - - - XXXXX
08h Years XXXXXXXX
09h Minute_alarm 1 XXXXXXX
0Ah Hour_alarm 1 - XXXXXX
0Bh Day_alarm 1 - XXXXXX
0Ch Weekday_alarm 1 ----XXX
0Dh CLKOUT_control -----000
0Eh Timer_control 0 -----11
0Fh Countdown_timer XXXXXXXX
Table 5. Register reset value
…continued
Bits labeled ‘-’ are not implemented and will return a ‘0’ when read. Bits labeled ‘X’ are undefined at
power-up and unchanged by subsequent resets.
Address Register name Bit
7 6 5 4 3 2 1 0
Fig 5. POR override sequence
001aaf900
minimum 500 ns minimum 2000 ns
POR override set at this time
SDI
CE
reset
override
minimum 500 ns

PCA2125TS/1,112

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
IC RTC CLK/CALENDAR SPI 14-TSSOP
Lifecycle:
New from this manufacturer.
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