OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

DS2174QN+

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24
1 of 24 091302
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.
GENERAL DESCRIPTION
The DS2174 enhanced bit error-rate tester
(EBERT) is a software-programmable test-pattern
generator, receiver, and analyzer capable of
meeting the most stringent error-performance
requirements of digital transmission facilities. It
features bit-serial, nibble-parallel, and byte-
parallel data interfaces, and generates and
uniquely synchronizes to pseudorandom patterns
of the form 2
n
- 1, where n can take on values from
1 to 32, and user-defined repetitive patterns of any
length up to 512 octets.
APPLICATIONS
§ Routers
§ Channel Service Units (CSUs)
§ Data Service Units (DSUs)
§ Muxes
§ Switches
§ Digital-to-Analog Converters (DACs)
§ CPE Equipment
§ Bridges
§ Smart Jack
PIN CONFIGURATION
FEATURES
§ Generates and detects digital patterns for
analyzing and trouble-shooting digital
communications systems
§ Programmable polynomial length and
feedback taps for generation of any
pseudorandom patterns up to 2
32
- 1; up to
32 taps can be used in the feedback path
§ Programmable, user-defined pattern
registers for long repetitive patterns up to
512 bytes in length
§ Large 48-bit count and bit error count
registers
§ Software-programmable bit error insertion
§ Fully independent transmit and receive
paths
§ 8-bit parallel-control port
§ Detects polynomial test patterns in the
presence of bit error rates up to 10
-2
§ Programmable for serial, 4-bit parallel, or
8-bit parallel data interfaces
§ Serial mode clock rate is 155MHz; byte
mode is 80MHz for a net 622Mbps; OC-3
§ Available in 44-pin PLCC
ORDERING INFORMATION
PART
TEMP
RANGE
PIN-
PACKAGE
DS2174Q 0°C to +70°C 44 PLCC
DS2174QN -40°C to +85°C 44 PLCC
www.maxim-ic.com
DS2174
EBERT
7
8
9
10
11
12
13
14
15
16
17
39
38
37
36
35
34
33
32
31
30
29
18
19
20
21
22
23
24
25
26
27
28
6
5
4
3
2
1
44
43
42
41
40
D2
D1
D0
TDAT7
TDAT6
GND
TDAT5
TDAT4
TDAT3
TDAT2
GND
RDAT3
RDAT4
RDAT5
RDAT6
RDAT7
GND
A0
A1
A2
A3
CS
RDAT2
RDAT1
RDAT0
RCLK_EN
RCLK
VDD
D7
D6
D5
D4
D3
RD
WR
TEST
TEST
GND
VDD
TCLK
TCLK_EN
TCLKO
TDAT0
TDAT1
DS2174
TOP VIEW
DS2174
2 of 24
.
TABLE OF CONTENTS
1. GENERAL OPERATION ................................................................................................................4
1.1 PATTERN GENERATION......................................................................................................................4
1.1.1 Polynomial Generation.......................................................................................... 4
1.1.2 Repetitive Pattern Generation ............................................................................... 4
1.2 PATTERN SYNCHRONIZATION ............................................................................................................5
1.2.1 Synchronization...................................................................................................... 5
1.2.2 Polynomial Synchronization .................................................................................. 5
1.2.3 Repetitive Pattern Synchronization ....................................................................... 5
1.3 BIT ERROR RATE (BER) CALCULATION............................................................................................5
1.3.1 Counters................................................................................................................. 5
1.4 GENERATING ERRORS .......................................................................................................................5
1.5 CLOCK DISCUSSION...........................................................................................................................6
1.6 POWER-UP SEQUENCE.......................................................................................................................6
1.7 DETAILED PIN DESCRIPTION .............................................................................................................8
2. PARALLEL CONTROL INTERFACE........................................................................................10
3. CONTROL REGISTERS ...............................................................................................................11
3.1 MODE SELECT .................................................................................................................................13
3.1.1 Error Insertion ..................................................................................................... 13
3.2 STATUS REGISTER ...........................................................................................................................15
3.3 PSEUDORANDOM PATTERN REGISTERS ...........................................................................................15
3.4 TEST REGISTER................................................................................................................................17
3.5 COUNT REGISTERS ..........................................................................................................................17
4. RAM ACCESS .................................................................................................................................18
4.1 INDIRECT ADDRESSING....................................................................................................................18
5. DC OPERATION ............................................................................................................................19
6. AC TIMING CHARACTERISTICS .............................................................................................20
6.1 PARALLEL PORT ..............................................................................................................................20
6.2 DATA INTERFACE ............................................................................................................................22
7. MECHANICAL DIMENSIONS ....................................................................................................24
DS2174
3 of 24
LIST OF FIGURES
FIGURE 1-1. BLOCK DIAGRAM.............................................................................................................. 6
FIGURE 6-1. READ TIMING ................................................................................................................... 20
FIGURE 6-2. WRITE TIMING.................................................................................................................. 21
FIGURE 6-3. TRANSMIT INTERFACE TIMING................................................................................... 22
FIGURE 6-4. RECEIVE INTERFACE TIMING ...................................................................................... 23
LIST OF TABLES
TABLE 1-A. PIN ASSIGNMENT ............................................................................................................... 7
TABLE 2-A. REGISTER MAP ................................................................................................................. 10
TABLE 3-A. MODE SELECT................................................................................................................... 13
TABLE 3-B. ERROR BIT INSERTION.................................................................................................... 13
TABLE 3-C. PSEUDORANDOM PATTERN GENERATION ............................................................... 16
TABLE 5-A. RECOMMENDED DC OPERATING CONDITIONS ....................................................... 19
TABLE 5-B. DC CHARACTERISTICS ................................................................................................... 19
TABLE 6-A. PARALLEL PORT READ TIMING ................................................................................... 20
TABLE 6-B. PARALLEL PORT WRITE TIMING.................................................................................. 21
TABLE 6-C. TRANSMIT DATA TIMING............................................................................................... 22
TABLE 6-D. RECEIVE DATA TIMING.................................................................................................. 23
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24

DS2174QN+

Mfr. #:
Buy DS2174QN+
Manufacturer:
Maxim Integrated
Description:
Telecom ICs Enhanced Bit Error Rate Tester (BERT)
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet