DS2174
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1.7 Detailed Pin Description
Signal Name: RCLK
Signal Description: Receive Clock
Signal Type: Input
Receive clock input. Up to a 155MHz clock to operate the receive circuit. Input data at RDATn is
sampled on the rising edge of RCLK.
Signal Name: RCLK_EN
Signal Description: Receive Clock Enable
Signal Type: Input
Gaps the RCLK input to the receive circuit.
Signal Name: RDAT0 to RDAT7
Signal Description: Receive Data Inputs
Signal Type: Input
RDAT0. Receive serial data/receive data bit 0 in nibble and byte mode
RDAT1. Receive data bit 1 in nibble and byte mode
RDAT2. Receive data bit 2 in nibble and byte mode
RDAT3. Receive data bit 3 in nibble and byte mode
RDAT4. Receive data bit 4 in byte mode
RDAT5. Receive data bit 5 in byte mode
RDAT6. Receive data bit 6 in byte mode
RDAT7. Receive data bit 7 in byte mode
Signal Name: A0 to A3
Signal Description: Address Inputs
Signal Type: Input
Address bus for addressing the control registers.
Signal Name: CS
Signal Description: Chip Select
Signal Type: Input
Active-low signal. Must be low to read or write to the part.
Signal Name: RD
Signal Description: Read Strobe
Signal Type: Input
Active-low signal. Must be low to read from the part.
Signal Name: WR
Signal Description: Write Strobe
Signal Type: Input
Active-low signal. Must be low to write to the part.
Signal Name: TEST
Signal Description: TEST Input
Signal Type: Input (with internal 10kΩ pullup)
Test Input. Should be left floating or held high.
