DS2174QN+ Datasheet DS2174Q, DS2174QN+ | P4-P6

DS2174

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1. GENERAL OPERATION

1.1 Pattern Generation

1.1.1 Polynomial Generation

The DS2174 has a tap select register that can be used as a mask to tap up to 32 bits in the feedback path

of the polynomial generator. It also features a seed register that can be used to preload the polynomial

generator with a seed value. This is done on the rising edge of TL in Control Register 1.

The DS2174 generates polynomial patterns of any length up to and including 2

- 1. All of the industry-

standard polynomials can be programmed using the control registers. The polynomial is generated using a

shift register of programmable length and programmable feedback tap positions. The user has access to

all combinations of pattern length and pattern tap location to generate industry-standard polynomials or

other combinations as well. In addition, the QRSS pattern described in T1.403 is described by the

polynomial 2

– 1. This pattern has the additional requirement that “an output bit is forced to a 1

whenever the next 14 bits are 0.” Setting the QRSS bit in Control Register 1 causes the pattern generator

to enforce this rule.

1.1.2 Repetitive Pattern Generation

In addition to polynomial patterns, the DS2174 generates repetitive patterns of considerable length. The

programmer has access to 512 bytes of memory for storing pattern. The pattern length bits PL0 through

PL8, located at addresses 02h and 03h, are used to program the length of the repetitive pattern. Memory is

addressed indirectly and is used to store the pattern. Data can be sent MSB or LSB first as it appears in

the memory.

Repetitive patterns can include simple patterns such as 3 in 24, but the additional memory can be used to

store patterns such as DDS-n patterns or T1-n patterns. Repetitive patterns are stored in increments of 8

bits. To generate a repetitive pattern that is 12 bits long (3 nibbles), the pattern is written twice such that

the pattern is 24 bits long (3 bytes), and repeats twice in memory. The same is true when the device is

used in serial mode: a 5-bit pattern is written to memory 5 times. For example,

To generate a 00001 pattern at the serial output, write these bytes to memory:

RAM ADDRESS BINARY CODE HEX CODE

00h 00010000 10h

01h 01000010 42h

02h 00001000 08h

03h 00100001 21h

04h 10000100 84h

DS2174

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1.2 Pattern Synchronization

1.2.1 Synchronization

The receiver synchronizes to the same pattern that is being transmitted. The pattern must be error free

when the synchronizer is online. Once synchronized, an error density of 6 bits in 64 causes the receiver to

declare loss-of-pattern sync, set the RLOS bit, and the synchronizer comes back online.

1.2.2 Polynomial Synchronization

Synchronization to polynomial patterns take 50 + n clock cycles (14 + n in nibble mode, 8 + n in byte

mode), where n is the exponent in the polynomial that describes the pattern. Once synchronized, any bit

that does not match the polynomial is counted as a bit error.

1.2.3 Repetitive Pattern Synchronization

Synchronization to repetitive patterns can take several complete repetitions of the entire pattern. The

actual sync time depends on the nature of the pattern and the location of the synchronization pointer.

Errors that occur during synchronization could affect the sync time; at least one complete error-free

repetition must be received before synchronization is declared. Once synchronized, any bit that does not

match the pattern that is programmed in the on-board RAM is counted as a bit error.

1.3 Bit Error Rate (BER) Calculation

1.3.1 Counters

The bit counter is active at all times. Once synchronized, the error counters come online. The receiver has

large 48-bit count registers. These counters accumulate for 50,640 hours at the T1 line rate, 1.544MHz,

and 38,170 hours at the E1 line rate, 2.048MHz. At higher clock rates, the counters saturate quicker, but

at the T3 line rate, the counter still runs for almost 1500 hours, and at 155MHz it runs for 504 hours.

To accumulate BER data, the user toggles the LC bit at T = 0. This clears the accumulators and loads the

contents into the count registers. At T = 0, these results should be ignored. At this point, the device is

counting bits and bit errors. At the end of the specified time interval, the user toggles the LC bit again and

reads the count registers. These are the valid results used to calculate a bit error rate. Remember, the bit

counter is really counting clocks, so in nibble and byte modes the bit counter value needs to be multiplied

by 4 or 8 to get the correct bit count. For longer integration periods, the results of multiple read cycles

have to be accumulated in software.

1.4 Generating Errors

Through Control Register 2, the user can intentionally inject a particular error rate into the transmitted

data stream. Injecting errors allows users to stress communication links and to check the functionality of

error monitoring equipment along the path.

DS2174

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1.5 Clock Discussion

There are two methods for moving test patterns through a telecom network.

1) The clock applied to TCLK and RCLK can be gapped by other devices on the target system. The

gapped clock would be applied to TCLK and RCLK only during the appropriate times. TDATn

outputs remain active during clock gaps.

2) The clock applied to TCLK and RCLK can be continuous at the applicable line rate and the

TCLK_EN and RCLK_EN pins can be asserted and deasserted during the appropriate time slots.

TDATn outputs remain active even when TCLK_EN is pulled low. The output level remains static at

the level of the last bit transmitted (output high for a 1, output low for a 0).

1.6 Power-Up Sequence

On power-up, the registers in the DS2174 are in a random state. The user must program all the internal

registers to a known state before proper operation can be ensured.

Figure 1-1. Block Diagram

BIT COUNTER

ERROR COUNTER

PATTERN DETECTOR

ERROR INSERTION

LOOPBACK MU

REPETITIVE PATTERN

GENERATOR

- 1

PARALLEL CONTROL PORT

RECEIVE

RATE

CONTROL

TRANSMIT

RATE

CONTROL

D[7:0]

CS RD

WR A[3:0]

RDAT[7:0]

TCLK0

TDAT[7:0]

TCLK

TCLK_EN

RCLK_EN

RCLK

SYNC

CR1.5

CR1.0

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24

DS2174QN+

Mfr. #:

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Manufacturer:

Maxim Integrated

Description:

Telecom ICs Enhanced Bit Error Rate Tester (BERT)

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DS2174QN+

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