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DS2174QN+

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DS2174
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Table 3-C. Pseudorandom Pattern Generation
PATTERN TYPE TAP0 TAP1 TAP2 TAP3 SEED0/1/2/3 TINV RINV
2
3
– 1 (Notes 1 and 2) 05 00 00 00 FF 0 0
2
4
– 1 (Note 1) 09 00 00 00 FF 0 0
2
5
– 1 (Note 1) 12 00 00 00 FF 0 0
2
6
– 1 (Note 1) 30 00 00 00 FF 0 0
2
7
– 1 Fractional T1 LB Activate
(Note 1)
48 00 00 00 FF 0 0
2
7
– 1 Fractional T1 LB
Deactivate (Note 1)
48 00 00 00 FF 1 1
2
7
– 1 (Note 1) 41 00 00 00 FF 0 0
2
8
– 1 Maximal Length B8 00 00 00 FF 0 0
2
9
– 1 O.153 (511 Type) 10 01 00 00 FF 0 0
2
10
– 1 40020000 FF 0 0
2
11
– 1 O.152 and O.153
(2047 Type)
00 05 00 00 FF 0 0
2
12
– 1 Maximal Length 29 08 00 00 FF 0 0
2
13
– 1 Maximal Length 0D 10 00 00 FF 0 0
2
14
– 1 Maximal Length 15 20 00 00 FF 0 0
2
15
– 1 O.151 00 60 00 00 FF 1 1
2
16
– 1 Maximal Length 08 D0 00 00 FF 0 0
2
17
– 1 04000100 FF 0 0
2
18
– 1 40000200 FF 0 0
2
19
– 1 Maximal Length 23 00 04 00 FF 0 0
2
20
– 1 O.153 04 00 08 00 FF 0 0
2
20
– 1 O.151 QRSS (CR1.3 = 1) 00 00 09 00 FF 0 0
2
21
– 1 02001000 FF 0 0
2
22
– 1 01002000 FF 0 0
2
23
– 1 O.151 00 00 42 00 FF 1 1
2
24
– 1 Maximal Length 00 00 E1 00 FF 0 0
2
25
– 1 04000001 FF 0 0
2
26
– 1 Maximal Length 23 00 00 02 FF 0 0
2
27
– 1 Maximal Length 13 00 00 04 FF 0 0
2
28
– 1 04000008 FF 0 0
2
29
– 1 02000010 FF 0 0
2
30
– 1 Maximal Length 29 00 00 20 FF 0 0
2
31
– 1 04000040 FF 0 0
2
32
– 1 Maximal Length 03 00 20 80 FF 0 0
Note 1: These pattern types do not work in byte mode.
Note 2: These pattern types do not work in nibble mode.
DS2174
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3.4 Test Register
Test register used for factory test. All bits must be set to 0 for proper operation.
Test Register (Address = 9h)
(MSB) (LSB)
TEST TEST TEST TEST TEST TEST TEST TEST
SYMBOL FUNCTION
TEST Factory Use. Must be set to 0 for proper operation.
TEST Factory Use. Must be set to 0 for proper operation.
TEST Factory Use. Must be set to 0 for proper operation.
TEST Factory Use. Must be set to 0 for proper operation.
TEST Factory Use. Must be set to 0 for proper operation.
TEST Factory Use. Must be set to 0 for proper operation.
TEST Factory Use. Must be set to 0 for proper operation.
TEST Factory Use. Must be set to 0 for proper operation.
3.5 Count Registers
Note: Bit 2 of Control Register 4 determines if the addresses point to the bit count or error count registers.
The bit count registers comprise a 48-bit count of bits (actually RCLK cycles) received at RDAT. C47 is
the MSB of the 48-bit count. The bit counter increments for each cycle of RCLK when RCLK_EN is
high. The bit counter is enabled regardless of synchronization. The status register bit BCOF is set when
this 48-bit register overflows. The counter rolls over upon an overflow condition. The DS2174 latches the
bit count into the bit count registers and clears the internal bit count when the LC bit in Control Register 1
is toggled from low to high.
The error count registers comprise a 48-bit count of bits received in error at RDAT. The bit error counter
is disabled during loss-of-sync. C47 is the MSB of the 48-bit count. The status register bit BECOF is set
when this 48-bit register overflows. The counter rolls over upon an overflow condition. The DS2174
latches the bit count into the bit error count registers and clears the internal bit error count when the LC
bit in Control Register 1 is toggled from low to high.
The bit count and bit error count registers are used by an external processor to compute the BER
performance on a loop or channel basis.
Count Registers (Address = Ah–Fh)
(MSB) (LSB)
C7 C6 C5 C4 C3 C2 C1 C0
C15 C14 C13 C12 C11 C10 C9 C8
C23 C22 C21 C20 C19 C18 C17 C16
C31 C30 C29 C28 C27 C26 C25 C24
C39 C38 C37 C36 C35 C34 C33 C32
C47 C46 C45 C44 C43 C42 C41 C40
DS2174
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4. RAM ACCESS
4.1 Indirect Addressing
512 bytes of memory, which is addressed indirectly, are available for repetitive patterns. Data bytes are
loaded one at a time into the indirect address register at address 0Fh. The RAM mode control bit, CR4.3,
determines the access to the RAM. If CR4.3 = 0, the RAM is under control of the BERT state machine. If
CR4.3 = 1, the RAM is under the control of the parallel port. This section discusses CR4.3 = 1.
The accompanying flow chart describes the algorithm used to write repetitive patterns to the RAM. The
programmer initializes a counter (n) to -1 in software, then sets CR4.3 and clears CR4.4. The rising edge
of CR4.3 resets the RAM address pointer to address 00h. Address 0Fh becomes the indirect access port to
the RAM. A write cycle on the parallel port to address 0Fh writes to the address in RAM pointed to by
the address pointer. The end of the write cycle, rising edge of WR, increments the address pointer. The
programmer then increments the counter (n) by 1 and loops until the pattern load is complete. Clear
CR4.3 to return control of the RAM to the BERT state machine. Finally, write the value in the counter (n)
back to address 04h and 05h to mark the last address of the pattern in memory.
The RAM contents can be verified by executing the same algorithm, replacing the parallel-port write with
a read, and setting CR4.4. CR4.3 must remain set for the entire algorithm to properly increment the
address pointer.
YES
WRITE n TO CR3
LAST BYTE?
DONE
CR4.3=1
CR4.4=0
n = -1
WRITE BYTE TO ADDRESS
0Fh
CR4.3 = 0
n = n + 1
START
NO
IF n > 255, THEN
SET CR4.0
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DS2174QN+

Mfr. #:
Buy DS2174QN+
Manufacturer:
Maxim Integrated
Description:
Telecom ICs Enhanced Bit Error Rate Tester (BERT)
Lifecycle:
New from this manufacturer.
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