DS2174
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6.2 Data Interface
Figure 6-3. Transmit Interface Timing
Table 6-C. TRANSMIT DATA TIMING
(V
DD
= 3.0V to 3.6V, T
A
= 0
°
C to +70°C for DS2174Q; V
DD
= 3.0V to 3.6V, T
A
= -40°C to +85°C
for DS2174QN)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
TCLK Clock Period (Nibble/Byte Mode) t
CYC
12.5 ns
TCLK High Time (Nibble/Byte Mode) t
PWH
5.0 ½ t
CYC
ns
TCLK Low Time (Nibble/Byte Mode) t
PWL
5.0 ½ t
CYC
ns
TCLK Clock Period (Bit Mode) t
CYC
6.45 ns 3
TCLK High Time (Bit Mode) t
PWH
2.0 ½ t
CYC
ns 3
TCLK Low Time (Bit Mode) t
PWL
2.0 ½ t
CYC
ns 3
TCLK_EN Setup Time Before TCLK
t
SU
2.5 ns
TCLK_EN Hold Time After TCLK
t
H
2.5 ns
TCLKO Output Delay After TCLK
t
OD
6.0 ns 1
TCLKO High Time (Nibble/Byte Mode) t
PWH(1)
5.0 ns 1
TCLKO High Time (Bit Mode) t
PWH(1)
2.0 ns 1, 3
TDAT Output Delay After TCLKO¯
t
OD(1)
5.0 ns 1, 2
NOTES:
1) 20pF load.
2) TDAT follows falling edge of TCLKO if CR4.5 = 0, rising edge if CR4.5 = 1.
3) Guaranteed by design.
TCLK
TDAT
TCLKO
TCLK_EN
t
CYC
t
PWH
t
PWL
t
H
t
SU
t
PWH(1)
t
OD
t
OD(1)
GAPPED CLOCK
GAPPED CLOCK
DATA OUT
