LPC2378FBD144,551 Datasheet LPC2378FBD144,551, LPC2377FBD144,551 | P19-P21

Product data sheet Rev. 6.1 — 16 October 2013 19 of 69

NXP Semiconductors

LPC2377/78

Single-chip 16-bit/32-bit microcontrollers

7.5 Interrupt controller

The ARM processor core has two interrupt inputs called Interrupt Request (IRQ) and Fast

Interrupt Request (FIQ). The VIC takes 32 interrupt request inputs which can be

programmed as FIQ or vectored IRQ types. The programmable assignment scheme

means that priorities of interrupts from the various peripherals can be dynamically

assigned and adjusted.

FIQs have the highest priority. If more than one request is assigned to FIQ, the VIC ORs

the requests to produce the FIQ signal to the ARM processor. The fastest possible FIQ

latency is achieved when only one request is classified as FIQ, because then the FIQ

service routine can simply start dealing with that device. But if more than one request is

assigned to the FIQ class, the FIQ service routine can read a word from the VIC that

identifies which FIQ source(s) is (are) requesting an interrupt.

Vectored IRQs, which include all interrupt requests that are not classified as FIQs, have a

programmable interrupt priority. When more than one interrupt is assigned the same

priority and occur simultaneously, the one connected to the lowest numbered VIC channel

will be serviced first.

The VIC ORs the requests from all of the vectored IRQs to produce the IRQ signal to the

ARM processor. The IRQ service routine can start by reading a register from the VIC and

jumping to the address supplied by that register.

7.5.1 Interrupt sources

Each peripheral device has one interrupt line connected to the VIC but may have several

interrupt flags. Individual interrupt flags may also represent more than one interrupt

source.

Any pin on Port 0 and Port 2 (total of 46 pins) regardless of the selected function, can be

programmed to generate an interrupt on a rising edge, a falling edge, or both. Such

interrupt requests coming from Port 0 and/or Port 2 will be combined with the EINT3

interrupt requests.

7.6 Pin connect block

The pin connect block allows selected pins of the microcontroller to have more than one

function. Configuration registers control the multiplexers to allow connection between the

pin and the on-chip peripherals.

Peripherals should be connected to the appropriate pins prior to being activated and prior

to any related interrupt(s) being enabled. Activity of any enabled peripheral function that is

not mapped to a related pin should be considered undefined.

7.7 External memory controller

The LPC2377/78 EMC is an ARM PrimeCell MultiPort Memory Controller peripheral

offering support for asynchronous static memory devices such as RAM, ROM, and flash.

In addition, it can be used as an interface with off-chip memory-mapped devices and

peripherals. The EMC is an Advanced Microcontroller Bus Architecture (AMBA) compliant

peripheral.

Product data sheet Rev. 6.1 — 16 October 2013 20 of 69

NXP Semiconductors

LPC2377/78

Single-chip 16-bit/32-bit microcontrollers

7.7.1 Features

• Asynchronous static memory device support including RAM, ROM, and flash, with or

without asynchronous page mode

• Low transaction latency

• Read and write buffers to reduce latency and to improve performance

• 8 data and 16 address lines wide static memory support

• Two chip selects for static memory devices

• Static memory features include:

– Asynchronous page mode read

– Programmable Wait States (WST)

– Bus turnaround delay

– Output enable and write enable delays

– Extended wait

7.8 General purpose DMA controller

The GPDMA is an AMBA AHB compliant peripheral allowing selected LPC2377/78

peripherals to have DMA support.

The GPDMA enables peripheral-to-memory, memory-to-peripheral,

peripheral-to-peripheral, and memory-to-memory transactions. Each DMA stream

provides unidirectional serial DMA transfers for a single source and destination. For

example, a bidirectional port requires one stream for transmit and one for receive. The

source and destination areas can each be either a memory region or a peripheral, and

can be accessed through the AHB master.

7.8.1 Features

• Two DMA channels. Each channel can support a unidirectional transfer.

• The GPDMA can transfer data between the 8 kB SRAM and peripherals such as the

SD/MMC, two SSP, and I

S-bus interfaces.

• Single DMA and burst DMA request signals. Each peripheral connected to the

GPDMA can assert either a burst DMA request or a single DMA request. The DMA

burst size is set by programming the GPDMA.

• Memory-to-memory, memory-to-peripheral, peripheral-to-memory, and

peripheral-to-peripheral transfers.

• Scatter or gather DMA is supported through the use of linked lists. This means that

the source and destination areas do not have to occupy contiguous areas of memory.

• Hardware DMA channel priority. Each DMA channel has a specific hardware priority.

DMA channel 0 has the highest priority and channel 1 has the lowest priority. If

requests from two channels become active at the same time, the channel with the

highest priority is serviced first.

• AHB slave DMA programming interface. The GPDMA is programmed by writing to the

DMA control registers over the AHB slave interface.

• One AHB master for transferring data. This interface transfers data when a DMA

request goes active.

Product data sheet Rev. 6.1 — 16 October 2013 21 of 69

NXP Semiconductors

LPC2377/78

Single-chip 16-bit/32-bit microcontrollers

• 32-bit AHB master bus width.

• Incrementing or non-incrementing addressing for source and destination.

• Programmable DMA burst size. The DMA burst size can be programmed to more

efficiently transfer data. Usually the burst size is set to half the size of the FIFO in the

peripheral.

• Internal four-word FIFO per channel.

• Supports 8-bit, 16-bit, and 32-bit wide transactions.

• An interrupt to the processor can be generated on a DMA completion or when a DMA

error has occurred.

• Interrupt masking. The DMA error and DMA terminal count interrupt requests can be

masked.

• Raw interrupt status. The DMA error and DMA count raw interrupt status can be read

prior to masking.

7.9 Fast general purpose parallel I/O

Device pins that are not connected to a specific peripheral function are controlled by the

GPIO registers. Pins may be dynamically configured as inputs or outputs. Separate

registers allow setting or clearing any number of outputs simultaneously. The value of the

output register may be read back as well as the current state of the port pins.

The LPC2377/78 use accelerated GPIO functions:

• GPIO registers are relocated to the ARM local bus so that the fastest possible I/O

timing can be achieved.

• Mask registers allow treating sets of port bits as a group, leaving other bits

unchanged.

• All GPIO registers are byte and half-word addressable.

• Entire port value can be written in one instruction.

Additionally, any pin on Port 0 and Port 2 (total of 46 pins) providing a digital function can

be programmed to generate an interrupt on a rising edge, a falling edge, or both. The

edge detection is asynchronous, so it may operate when clocks are not present such as

during Power-down mode. Each enabled interrupt can be used to wake up the chip from

Power-down mode.

7.9.1 Features

• Bit level set and clear registers allow a single instruction to set or clear any number of

bits in one port.

• Direction control of individual bits.

• All I/O default to inputs after reset.

• Backward compatibility with other earlier devices is maintained with legacy Port 0 and

Port 1 registers appearing at the original addresses on the APB bus.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P39 P40-P42 P43-P45 P46-P48 P49-P51 P52-P54 P55-P57 P58-P60 P61-P63 P64-P66 P67-P69

LPC2378FBD144,551

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ARM Microcontrollers - MCU ARM7 512KF/USB/ENET

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LPC2378FBD144,551

LPC2378FBD144,551

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