LPC2377_78 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 6.1 — 16 October 2013 4 of 69
NXP Semiconductors
LPC2377/78
Single-chip 16-bit/32-bit microcontrollers
5. Block diagram
(1) LPC2378 only.
Fig 1. LPC2377/78 block diagram
power domain 2
LPC2377/78
A[15:0]
D[7:0]
EXTERNAL
MEMORY
CONTROLLER
ALARM
002aac574
PWM1
ARM7TDMI-S
PLL
EINT3 to EINT0
FLASH
P3, P4
P0, P1, P2,
LEGACY GPI/O
56 PINS TOTAL
P0, P1
SCK, SCK0
MOSI, MOSI0
SSEL, SSEL0
SCK1
MOSI1
MISO1
SSEL1
SCL0, SCL1, SCL2
I2SRX_CLK
I2STX_CLK
I2SRX_WS
I2STX_WS
8 × AD0
RTCX1
RTCX2
MCICLK, MCIPWR
RXD0, RXD2, RXD3
TXD1
RXD1
RD1, RD2
TD1, TD2
CAN1, CAN2
(1)
2 × USB_D+/USB_D
XTAL1
TCK TDO
EXTIN0
XTAL2
TRST
TDITMS
HIGH-SPEED
GPI/O
104 PINS
TOTAL
32 kB
SRAM
512 kB
FLASH
INTERNAL
CONTROLLERS
TEST/DEBUG
INTERFACE
EMULATION
TRACE MODULE
trace signals
AHB
BRIDGE
AHB
BRIDGE
ETHERNET
MAC WITH
DMA
16 kB
SRAM
MASTER
PORT
AHB TO
AHB BRIDGE
SLAVE
PORT
system
clock
SYSTEM
FUNCTIONS
INTERNAL RC
OSCILLATOR
V
DDA
V
DD(3V3)
V
DD(DCDC)(3V3)
VREF
V
SSA
, V
SS
VECTORED
INTERRUPT
CONTROLLER
8 kB
SRAM
USB WITH
4 kB RAM
AND DMA
(1)
GP DMA
CONTROLLER
I
2
S INTERFACE
SPI, SSP0 INTERFACE
I2SRX_SDA
I2STX_SDA
MISO, MISO0
SSP1 INTERFACE
SD/MMC CARD
INTERFACE
MCICMD,
MCIDAT[3:0]
TXD0, TXD2, TXD3
UART0, UART2, UART3
UART1
DTR1, RTS1
DSR1, CTS1, DCD1,
RI1
I
2
C0, I
2
C1, I
2
C2
SDA0, SDA1, SDA2
EXTERNAL INTERRUPTS
CAPTURE/COMPARE
TIMER0/TIMER1/
TIMER2/TIMER3
A/D CONVERTER
D/A CONVERTER
2 kB BATTERY RAM
RTC
OSCILLATOR
REAL-
TIME
CLOCK
WATCHDOG TIMER
SYSTEM CONTROL
2 × CAP0/CAP1/
CAP2/CAP3
4 × MAT2,
2 × MAT0/MAT1/
MAT3
6 × PWM1
2 × PCAP1
AOUT
VBAT
AHB TO
APB BRIDGE
SRAM
RMII(8)
RESET
V
BUS
2 × USB_CONNECT
2 × USB_UP_LED
DBGEN
P0, P2
AHB2 AHB1
OE, CS0, CS1,
BLS0
LPC2377_78 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 6.1 — 16 October 2013 5 of 69
NXP Semiconductors
LPC2377/78
Single-chip 16-bit/32-bit microcontrollers
6. Pinning information
6.1 Pinning
Fig 2. LPC2377/78 pinning
LPC2377FBD144
LPC2378FBD144
108
37
72
144
109
73
1
36
002aac584
LPC2377_78 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 6.1 — 16 October 2013 6 of 69
NXP Semiconductors
LPC2377/78
Single-chip 16-bit/32-bit microcontrollers
6.2 Pin description
Table 3. Pin description
Symbol Pin Type Description
P0[0] to P0[31] I/O Port 0: Port 0 is a 32-bit I/O port with individual direction controls for each bit. The
operation of port 0 pins depends upon the pin function selected via the pin connect
block.
P0[0]/RD1/TXD/
SDA1
66
[1]
I/O P0[0] — General purpose digital input/output pin.
I RD1 — CAN1 receiver input. (LPC2378 only)
O TXD3 — Transmitter output for UART3.
I/O SDA1 — I
2
C1 data input/output (this pin is not open-drain).
P0[1]/TD1/RXD3/
SCL1
67
[1]
I/O P0[1] — General purpose digital input/output pin.
O TD1 — CAN1 transmitter output. (LPC2378 only)
I RXD3 — Receiver input for UART3.
I/O SCL1 — I
2
C1 clock input/output (this pin is not open-drain).
P0[2]/TXD0 141
[1]
I/O P0[2] — General purpose digital input/output pin.
O TXD0 — Transmitter output for UART0.
P0[3]/RXD0 142
[1]
I/O P0[3] — General purpose digital input/output pin.
I RXD0 — Receiver input for UART0.
P0[4]/
I2SRX_CLK/
RD2/CAP2[0]
116
[1]
I/O P0[4] — General purpose digital input/output pin.
I/O I2SRX_CLK — Receive Clock. It is driven by the master and received by the slave.
Corresponds to the signal SCK in the I
2
S-bus specification.
I RD2 — CAN2 receiver input. (LPC2378 only)
I CAP2[0] — Capture input for Timer 2, channel 0.
P0[5]/
I2SRX_WS/
TD2/CAP2[1]
115
[1]
I/O P0[5] — General purpose digital input/output pin.
I/O I2SRX_WS — Receive Word Select. It is driven by the master and received by the
slave. Corresponds to the signal WS in the I
2
S-bus specification.
O TD2 — CAN2 transmitter output. (LPC2378 only)
I CAP2[1] — Capture input for Timer 2, channel 1.
P0[6]/
I2SRX_SDA/
SSEL1/MAT2[0]
113
[1]
I/O P0[6] — General purpose digital input/output pin.
I/O I2SRX_SDA — Receive data. It is driven by the transmitter and read by the
receiver. Corresponds to the signal SD in the I
2
S-bus specification.
I/O SSEL1 — Slave Select for SSP1.
O MAT2[0] — Match output for Timer 2, channel 0.
P0[7]/
I2STX_CLK/
SCK1/MAT2[1]
112
[1]
I/O P0[7] — General purpose digital input/output pin.
I/O I2STX_CLK — Transmit Clock. It is driven by the master and received by the slave.
Corresponds to the signal SCK in the I
2
S-bus specification.
I/O SCK1 — Serial Clock for SSP1.
O MAT2[1] — Match output for Timer 2, channel 1.
P0[8]/
I2STX_WS/
MISO1/MAT2[2]
111
[1]
I/O P0[8] — General purpose digital input/output pin.
I/O I2STX_WS — Transmit Word Select. It is driven by the master and received by the
slave. Corresponds to the signal WS in the I
2
S-bus specification.
I/O MISO1 — Master In Slave Out for SSP1.
O MAT2[2] — Match output for Timer 2, channel 2.

LPC2378FBD144,551

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
ARM Microcontrollers - MCU ARM7 512KF/USB/ENET
Lifecycle:
New from this manufacturer.
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