LPC2377_78 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 6.1 — 16 October 2013 22 of 69
NXP Semiconductors
LPC2377/78
Single-chip 16-bit/32-bit microcontrollers
7.10 Ethernet
The Ethernet block contain a full featured 10 Mbit/s or 100 Mbit/s Ethernet MAC designed
to provide optimized performance through the use of DMA hardware acceleration.
Features include a generous suite of control registers, half or full duplex operation, flow
control, control frames, hardware acceleration for transmit retry, receive packet filtering
and wake-up on LAN activity. Automatic frame transmission and reception with
scatter-gather DMA off-loads many operations from the CPU.
The Ethernet block and the CPU share a dedicated AHB subsystem that is used to access
the Ethernet SRAM for Ethernet data, control, and status information. All other AHB traffic
in the LPC2377/78 takes place on a different AHB subsystem, effectively separating
Ethernet activity from the rest of the system. The Ethernet DMA can also access off-chip
memory via the EMC, as well as the SRAM located on another AHB, if it is not being used
by the USB block. However, using memory other than the Ethernet SRAM, especially
off-chip memory, will slow Ethernet access to memory and increase the loading of its AHB.
The Ethernet block interfaces between an off-chip Ethernet PHY using the Reduced MII
(RMII) protocol and the on-chip Media Independent Interface Management (MIIM) serial
bus.
7.10.1 Features
• Ethernet standards support:
– Supports 10 Mbit/s or 100 Mbit/s PHY devices including 10 Base-T, 100 Base-TX,
100 Base-FX, and 100 Base-T4.
– Fully compliant with IEEE standard 802.3.
– Fully compliant with 802.3x full duplex flow control and half duplex back pressure.
– Flexible transmit and receive frame options.
– Virtual Local Area Network (VLAN) frame support.
• Memory management:
– Independent transmit and receive buffers memory mapped to shared SRAM.
– DMA managers with scatter/gather DMA and arrays of frame descriptors.
– Memory traffic optimized by buffering and pre-fetching.
• Enhanced Ethernet features:
– Receive filtering.
– Multicast and broadcast frame support for both transmit and receive.
– Optional automatic Frame Check Sequence (FCS) insertion with Circular
Redundancy Check (CRC) for transmit.
– Selectable automatic transmit frame padding.
– Over-length frame support for both transmit and receive allows any length frames.
– Promiscuous receive mode.
– Automatic collision back-off and frame retransmission.
– Includes power management by clock switching.
– Wake-on-LAN power management support allows system wake-up: using the
receive filters or a magic frame detection filter.
