CS5461A
22 DS661F3
5.13 Serial Port Overview
The CS5461A incorporates a serial port transmit and re-
ceive buffer with a command decoder that interprets
one-byte (8 bits) commands as they are received. There
are four types of commands; instructions, synchroniz-
ing, register writes and register reads (See Section 5.14
Commands on page 23).
Instructions are one byte in length and will interrupt any
instruction currently executing. Instructions do not affect
register reads currently being transmitted.
Synchronizing commands are one byte in length and
only affect the serial interface. Synchronizing com-
mands do not affect operations currently in progress.
Register writes must be followed by three bytes of data.
register reads can return up to four bytes of data.
Commands and data are transferred most-significant bit
(MSB) first. Figure 1 on page 11, defines the serial port
timing and required sequence necessary to write to and
read from the serial port receive and transmit buffer, re-
spectively. While reading data from the serial port, com-
mands and data can be simultaneously written. Starting
a new register read command while data is being read
will terminate the current read in progress. This is ac-
ceptable if the remainder of the current read data is not
needed. During data reads, the serial port requires input
data. If a new command and data is not sent, SYNC0 or
SYNC1 must be sent.
5.13.1 Serial Port Interface
The serial port interface is a “4-wire” synchronous serial
communications interface. The interface is enabled to
start excepting SCLKs when CS
(Chip Select) is assert-
ed. SCLK (Serial bit-clock) is a Schmitt-trigger input that
is used to strobe the data on SDI (Serial Data In) into the
receive buffer and out of the transmit buffer onto SDO
(Serial Data Out).
If the serial port interface becomes unsynchronized with
respect to the SCLK input, any attempt to clock valid
commands into the serial interface may result in unex-
pected operation. The serial port interface must then be
re-initialized by one of the following actions:
- Drive the CS
pin high, then low.
- Hardware Reset (drive RESET
pin low, for at
least 10 µs).
- Issue the Serial Port Initialization Sequence,
which is 3 (or more) SYNC1 command bytes
(0xFF) followed by one SYNC0 command byte
(0xFE).
If a resynchronization is necessary, it is best to re-initial-
ize the part either by hardware or software reset (0x80),
as the state of the part may be unknown.
CS5461A
DS661F3 23
5.14 Commands
All commands are 8-bits in length. Any byte that is not listed in this section is invalid. Commands that write to regis-
ters must be followed by 3 bytes of data. Commands that read data can be chained with other commands (e.g., while
reading data, a new command can be sent which can execute during the original read). All commands except reg-
ister reads, register writes, and SYNC0 & SYNC1 will abort any currently executing commands.
5.14.1 Start Conversions
Initiates acquiring measurements and calculating results. The device has three modes of acquisition.
C[3:2] Modes of acquisition/measurement
00 = Perform a single computation cycle
01 = Not Used
10 = Perform continuous computation cycles
11 = Perform continuous computation cycles with APF enabled on the other channel
5.14.2 SYNC0 and SYNC1
The serial port can be initialized by asserting CS or by sending three or more consecutive SYNC1 commands fol-
lowed by a SYNC0 command. The SYNC0 or SYNC1 can also be sent while sending data out.
SYNC 0 = Last byte of a serial port re-initialization sequence.
1 = Used during reads and serial port initialization.
5.14.3 Power-Up/Halt
If the device is powered-down, Power-Up/Halt will initiate a power on reset. If the part is already powered-on, all
computations will be halted.
5.14.4 Power-down and Software Reset
To conserve power the CS5461A has two power-down states. In stand-by state all circuitry, except the analog/digital
clock generators, is turned off. In the sleep state all circuitry, except the instruction decoder, is turned off. Bringing
the CS5461A out of sleep state requires more time than out of stand-by state, because of the extra time needed to
re-start and re-stabilize the analog oscillator.
S[1:0] Power-down state
00 = Software Reset
01 = Halt and enter stand-by power saving state. This state allows quick power-on
10 = Halt and enter sleep power saving state.
11 = Reserved
B7 B6 B5 B4 B3 B2 B1 B0
1110C3C200
B7 B6 B5 B4 B3 B2 B1 B0
1111111SYNC
B7 B6 B5 B4 B3 B2 B1 B0
10100000
B7 B6 B5 B4 B3 B2 B1 B0
100S1S0000
CS5461A
24 DS661F3
5.14.5 Register Read/Write
The Read/Write informs the command decoder that a register access is required. During a read operation, the ad-
dressed register is loaded into an output buffer and clocked out by SCLK. During a write operation, the data is
clocked into an input buffer and transferred to the addressed register upon completion of the 24
th
SCLK.
W/R
Write/Read control
0 = Read
1 = Write
RA[4:0] Register address bits (bits 5 through 1) of the read/write command.
Address
RA[4:0] Name Description
0 00000 Config Configuration
1 00001 I
DCoff Current DC Offset
2 00010 I
gn Current Gain
3 00011 V
DCoff Voltage DC Offset
4 00100 V
gn Voltage Gain
5 00101 Cycle Count Number of A/D conversions used in one computation cycle (N)).
6 00110 PulseRateE
1,2
Sets the E1 and E2 energy-to-frequency output pulse rate.
7 00111 I Instantaneous Current
8 01000 V Instantaneous Voltage
9 01001 P Instantaneous Power
10 01010 P
Active Active (Real) Power
11 01011 I
RMS
RMS Current
12 01100 V
RMS
RMS Voltage
14 01110 P
off Power Offset
15 01111 Status Status
16 10000 I
ACoff Current AC (RMS) Offset
17 10001 V
ACoff Voltage AC (RMS) Offset
18 10010 PulseRateE
3
Sets the E3 energy-to-frequency output pulse rate.
19 10011 T Temperature
20 10100 SYS
Gain
System Gain
21 10101 PW Pulse width register for mechanical counter output mode
22 10110 PulseWidth Pulse width register for E3
energy pulse output
23 10111 VSAG
Duration Voltage Sag Duration
24 11000 VSAG
Level Voltage Sag Level Threshold
25 11001 LoadIntv No load threshold interval (detection window)
26 11010 Mask Interrupt Mask
27 11011 LoadMin No Load Threshold
28 11100 Ctrl Control
29 11101 T
Gain
Temperature Sensor Gain
30 11110 T
off
Temperature Sensor Offset
31 11111 S Apparent Power
Note: For proper operation, do not attempt to write to unspecified registers.
B7 B6 B5 B4 B3 B2 B1 B0
0W/R
RA4 RA3 RA2 RA1 RA0 0

CS5461A-ISZR

Mfr. #:
Manufacturer:
Cirrus Logic
Description:
Current & Power Monitors & Regulators IC Sngl-Phs BiDirect PWR/Energy
Lifecycle:
New from this manufacturer.
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