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CS5461A-ISZR

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P44
CS5461A
28 DS661F3
6.5 PulseRateE
1,2
Register
Address: 6
Default = 0xFA000 = 32000.00 Hz
PulseRateE
1,2
sets the frequency of the E1 and/or E2 pulses. The smallest valid frequency is 2
-4
with 2
-5
incre-
mental steps. A pulse rate higher than (MCLK/K)/8 will result in a pulse rate setting of (MCLK/K)/8. The value
is represented in unsigned notation, with the binary point to the right of bit 5.
6.6 Instantaneous Current, Voltage and Power Registers ( I , V , P )
Address: 7 (Instantaneous Current); 8 (Instantaneous Voltage); 9 (Instantaneous Power)
I and V contain the instantaneous measured values for current and voltage, respectively. The instantaneous
voltage and current samples are multiplied to obtain Instantaneous Power (P). The value is represented in two's
complement notation and in the range of -1.0 I, V, P 1.0, with the binary point to the right of the MSB.
6.7 Active (Real) Power Registers ( P
Active
)
Address: 10
The instantaneous power is averaged over each computation cycle (N conversions) to compute Active Power
(P
Active
). The value is represented in two's complement notation and in the range of -1.0 P
Active
1.0, with the
binary point to the right of the MSB.
6.8 I
RMS
and V
RMS
Registers ( I
RMS
, V
RMS
)
Address: 11 (I
RMS
); 12 (V
RMS
)
I
RMS
and V
RMS
contain the Root Mean Square (RMS) value of I and V, calculated over each computation cycle.
The value is represented in unsigned binary notation and in the range of 0.0 I
RMS
,V
RMS
1.0, with the binary
point to the left of the MSB.
6.9 Power Offset Register ( P
off
)
Address: 14
Default = 0x000000
Power Offset (P
off
) is added to the instantaneous power being accumulated in the P
active
register and can be
used to offset contributions to the energy result that are caused by undesirable sources of energy that are in-
herent in the system. The value is represented in two's complement notation and in the range of -1.0 P
off 1.0,
with the binary point to the right of the MSB.
MSB LSB
2
18
2
17
2
16
2
15
2
14
2
13
2
12
2
11
.....
2
1
2
0
2
-1
2
-2
2
-3
2
-4
2
-5
MSB LSB
-(2
0
)2
-1
2
-2
2
-3
2
-4
2
-5
2
-6
2
-7
.....
2
-17
2
-18
2
-19
2
-20
2
-21
2
-22
2
-23
MSB LSB
-(2
0
)2
-1
2
-2
2
-3
2
-4
2
-5
2
-6
2
-7
.....
2
-17
2
-18
2
-19
2
-20
2
-21
2
-22
2
-23
MSB LSB
2
-1
2
-2
2
-3
2
-4
2
-5
2
-6
2
-7
2
-8
.....
2
-18
2
-19
2
-20
2
-21
2
-22
2
-23
2
-24
MSB LSB
-(2
0
)2
-1
2
-2
2
-3
2
-4
2
-5
2
-6
2
-7
.....
2
-17
2
-18
2
-19
2
-20
2
-21
2
-22
2
-23
CS5461A
DS661F3 29
6.10 Status Register and Mask Register ( Status , Mask )
Address: 15 (Status); 26 (Mask)
Default = 0x000001 (Status Register), 0x000000 (Mask Register)
The Status Register indicates status within the chip. In normal operation, writing a '1' to a bit will cause the bit
to reset. Writing a '0' to a bit will not change it’s current state.
The Mask Register is used to control the activation of the INT
pin. Placing a logic '1' in a Mask bit will allow the
corresponding bit in the Status Register to activate the INT
pin when the status bit is asserted.
DRDY Data Ready. During conversions, this bit will indicate the end of computation cycles. For cali-
brations, this bit indicates the end of a calibration sequence.
CRDY Conversion Ready. Indicates a new conversion is ready. This will occur at the output word rate.
IOR Current Out of Range. Set when the Instantaneous Current Register overflows.
VOR Voltage Out of Range. Set when the Instantaneous Voltage Register overflows.
IROR I
RMS
Out of Range. Set when the I
RMS
Register overflows.
VROR V
RMS
Out of Range. Set when the V
RMS
Register overflows.
EOR Energy Out of Range. Set when P
ACTIVE
overflows.
TUP Temperature Updated. Indicates the Temperature Register has updated.
TOD Modulator oscillation detected on the temperature channel. Set when the modulator oscillates
due to an input above full scale.
VOD (IOD) Modulator oscillation detected on the voltage (current) channel. Set when the modulator oscil-
lates due to an input above full scale. The level at which the modulator oscillates is significantly
higher than the voltage (current) channel’s differential input voltage range.
Note: The IOD and VOD bits may be ‘falsely’ triggered by very brief voltage spikes from the
power line. This event should not be confused with a DC overload situation at the in-
puts, when the IOD and VOD bits will re-assert themselves even after being cleared,
multiple times.
LSD Low Supply Detect. Set when the voltage at the PFMON pin falls below the low-voltage thresh-
old (PMLO), with respect to AGND pin. The LSD bit cannot be reset until the voltage at PFMON
pin rises back above the high-voltage threshold (PMHI).
VSAG Indicates a voltage sag has occurred. See Section 5.5 Voltage Sag-detect Feature on page 19.
IC
Invalid Command. Normally logic 1. Set to logic 0 if an invalid command is received or the Sta-
tus Register has not been successfully read.
23 22 21 20 19 18 17 16
DRDY CRDY IOR VOR
15 14 13 12 11 10 9 8
IROR VROR EOR
76543210
TUP TOD VOD IOD LSD VSAG
IC
CS5461A
30 DS661F3
6.11 Current and Voltage AC Offset Register ( V
ACoff
, I
ACoff
)
Address: 16 (Current AC Offset); 17 (Voltage AC Offset)
Default = 0x000000
The AC Offset Registers (V
ACoff, IACoff) are initialized to zero on reset, allowing for uncalibrated normal operation.
AC Offset Calibration updates these registers. This sequence lasts approximately (6N + 30) ADC cycles (where
N is the value of the Cycle Count Register). DRDY will be asserted at the end of the calibration. These values
may be read and stored for future system AC offset compensation. The value is represented in two's comple-
ment notation and in the range of -1.0 V
ACoff, IACoff 1.0, with the binary point to the right of the MSB.
6.12 PulseRateE
3
Register
Address: 18
Default = 0xFA0000 = 32000.00 Hz
PulseRateE
3
sets the frequency of the E3 pulses. The register’s smallest valid frequency is 2
-4
with 2
-5
incre-
mental steps. A pulse rate higher than (MCLK/K)/8 will result in a pulse rate setting of (MCLK/K)/8. The value
is represented in unsigned notation, with the binary point to the right of bit #5.
6.13 Temperature Register ( T )
Address: 19
T contains measurements from the on-chip temperature sensor. Measurements are performed during continu-
ous conversions, with the default the Celsius scale (
o
C). The value is represented in two's complement notation
and in the range of -128.0 T 128.0, with the binary point to the right of the eighth MSB.
6.14 System Gain Register ( SYS
Gain
)
Address: 20
Default = 0x500000 = 1.25
System Gain (SYS
Gain) determines the one’s density of the channel measurements. Small changes in the mod-
ulator due to temperature can be fine adjusted by changing the system gain. The value is represented in two's
complement notation and in the range of -2.0 SYS
Gain 2.0, with the binary point to the right of the second
MSB.
MSB LSB
-(2
0
)2
-1
2
-2
2
-3
2
-4
2
-5
2
-6
2
-7
.....
2
-17
2
-18
2
-19
2
-20
2
-21
2
-22
2
-23
MSB LSB
2
18
2
17
2
16
2
15
2
14
2
13
2
12
2
11
.....
2
1
2
0
2
-1
2
-2
2
-3
2
-4
2
-5
MSB LSB
-(2
7
)2
6
2
5
2
4
2
3
2
2
2
1
2
0
.....
2
-10
2
-11
2
-12
2
-13
2
-14
2
-15
2
-16
MSB LSB
-(2
1
)2
0
2
-1
2
-2
2
-3
2
-4
2
-5
2
-6
.....
2
-16
2
-17
2
-18
2
-19
2
-20
2
-21
2
-22
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P44

CS5461A-ISZR

Mfr. #:
Buy CS5461A-ISZR
Manufacturer:
Cirrus Logic
Description:
Current & Power Monitors & Regulators IC Sngl-Phs BiDirect PWR/Energy
Lifecycle:
New from this manufacturer.
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