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CS5461A-ISZR

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P44
CS5461A
DS661F3 7
3. CHARACTERISTICS & SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS
ANALOG CHARACTERISTICS
• Min / Max characteristics and specifications are guaranteed over all Recommended Operating Conditions.
• Typical characteristics and specifications are measured at nominal supply voltages and TA = 25 °C.
• VA+ = VD+ = 5 V ±5%; AGND = DGND = 0 V; VREFIN = +2.5 V. All voltages with respect to 0 V.
• MCLK = 4.096 MHz.
Parameter Symbol Min Typ Max Unit
Positive Digital Power Supply VD+ 3.135 5.0 5.25 V
Positive Analog Power Supply VA+ 4.75 5.0 5.25 V
Voltage Reference VREFIN - 2.5 - V
Specified Temperature Range T
A
-40 - +85 °C
Parameter Symbol Min Typ Max Unit
Linearity Performance
Active Power Accuracy (All Gain Ranges)
(Note 1) Input Range 0.1% - 100%
P
Active
-±0.1- %
Current RMS Accuracy (All Gain Ranges)
(Note 1) Input Range 0.2% - 100%
Input Range 0.1% - 0.2%
I
RMS
-
-
±0.2
±1.5
-
-
%
%
Voltage RMS Accuracy (All Gain Ranges)
(Note 1) Input Range 5% - 100%
V
RMS
-±0.1- %
Analog Inputs (Both Channels)
Common Mode Rejection (DC, 50, 60 Hz) CMRR 80 - - dB
Common Mode + Signal (All Gain Ranges) -0.25 - VA+ V
Analog Inputs (Current Channel)
Differential Input Range (Gain = 10)
[(IIN+) - (IIN-)] (Gain = 50)
IIN
-
-
500
100
-
-
mV
P-P
mV
P-P
Total Harmonic Distortion (Gain = 50) THD 80 94 - dB
Crosstalk with Voltage Channel at Full Scale (50, 60 Hz) - -115 - dB
Input Capacitance (Gain = 10)
(Gain = 50)
IC
-
-
32
52
-
-
pF
pF
Effective Input Impedance EII 30 - - k
Noise (Referred to Input) (Gain = 10)
(Gain = 50)
N
I
-
-
22.5
4.5
-
-
µV
rms
µV
rms
Offset Drift (Without the high-pass filter) OD - 4.0 - µV/°C
Gain Error (Note 2) GE - ±0.4 %
Analog Inputs (Voltage Channel)
Differential Input Range {(VIN+) - (VIN-)}
VIN
-500-mV
P-P
Total Harmonic Distortion THD 65 75 - dB
Crosstalk with Current Channel at Full Scale (50, 60 Hz) - -70 - dB
Input Capacitance All Gain Ranges IC - 0.2 - pF
Effective Input Impedance EII 2 - - M
Noise (Referred to Input) N
V
-140-µV
rms
Offset Drift (Without the high-pass Filter) OD - 16.0 - µV/°C
Gain Error (Note 2) GE - ±3.0 %
CS5461A
8 DS661F3
ANALOG CHARACTERISTICS (Continued)
1. Applies when the HPF option is enabled.
2. Applies before system calibration.
3. All outputs unloaded. All inputs CMOS level.
4. Measurement method for PSRR: VREFIN tied to VREFOUT, VA+ = VD+ = 5 V, a 150 mV (zero-to-peak) (60 Hz)
sinewave is imposed onto the +5 V DC supply voltage at VA+ and VD+ pins. The “+” and “-” input pins of both input
channels are shorted to AGND. Then the CS5461A is commanded to continuous conversion acquisition mode, and
digital output data is collected for the channel under test. The (zero-to-peak) value of the digital sinusoidal output
signal is determined, and this value is converted into the (zero-to-peak) value of the sinusoidal voltage (measured
in mV) that would need to be applied at the channel’s inputs, in order to cause the same digital sinusoidal output.
This voltage is then defined as Veq. PSRR is then (in dB)
:
5. When voltage level on PFMON is sagging, and LSD bit is at 0, the voltage at which LSD bit is set to 1.
6. If the LSD bit has been set to 1 (because PFMON voltage fell below PMLO), this is the voltage level on PFMON at
which the LSD bit can be permanently reset back to 0.
VOLTAGE REFERENCE
Notes: 7. The voltage at VREFOUT is measured across the temperature range. From these measurements the following
formula is used to calculate the VREFOUT Temperature Coefficient:.
8. Specified at maximum recommended output of 1 µA, source or sink.
Parameter Symbol Min Typ Max Unit
Temperature Channel
Temperature Accuracy T - ±5 - °C
Power Supplies
Power Supply Currents (Active State) I
A+
I
D+
(VA+ = VD+ = 5 V)
I
D+
(VA+ = 5 V, VD+ = 3.3 V)
PSCA
PSCD
PSCD
-
-
-
1.1
2.9
1.7
-
-
-
mA
mA
mA
Power Consumption Active State (VA+ = VD+ = 5 V)
(Note 3) Active State (VA+ = 5 V, VD+ = 3.3 V)
Stand-By State
Sleep State
PC
-
-
-
-
21
12
8
10
28
16.5
-
-
mW
mW
mW
µW
Power Supply Rejection Ratio (DC, 50 and 60 Hz)
(Note 4) Voltage Channel
Current Channel
PSRR
45
70
65
75
-
-
dB
dB
PFMON Low-voltage Trigger Threshold (Note 5) PMLO 2.3 2.45 - V
PFMON High-voltage Power-On Trip Point (Note 6) PMHI - 2.55 2.7 V
Parameter Symbol Min Typ Max Unit
Reference Output
Output Voltage VREFOUT +2.4 +2.5 +2.6 V
Temperature Coefficient (Note 7) TC
VREF
- 25 60 ppm/°C
Load Regulation (Note 8) V
R
-610mV
Reference Input
Input Voltage Range VREFIN +2.4 +2.5 +2.6 V
Input Capacitance - 4 - pF
Input CVF Current - 25 - nA
PSRR 20
150
V
eq
----------



log=
(VREFOUTMAX - VREFOUTMIN)
VREFOUT
AVG
(
(
1
T
A
MAX
- T
A
MIN
(
(
1.0 x 10
(
(
6
TC
VREF
=
CS5461A
DS661F3 9
DIGITAL CHARACTERISTICS
• Min / Max characteristics and specifications are guaranteed over all Recommended Operating Conditions.
• Typical characteristics and specifications are measured at nominal supply voltages and TA = 25 °C.
• VA+ = VD+ = 5V ±5%; AGND = DGND = 0 V. All voltages with respect to 0 V.
• MCLK = 4.096 MHz.
Notes: 9. All measurements performed under static conditions.
10. If a crystal is used, then XIN frequency must remain between 2.5 MHz - 5.0 MHz. If an external oscillator is used,
XIN frequency range is 2.5 MHz - 20 MHz, but K must be set so that MCLK is between 2.5 MHz - 5.0 MHz.
11. If external MCLK is used, then the duty cycle must be between 45% and 55% to maintain this specification.
12. The frequency of CPUCLK is equal to MCLK.
13. The minimum FSCR is limited by the maximum allowed gain register value. The maximum FSCR is limited by the
full-scale signal applied to the channel input.
14. Configuration Register bits PC[6:0] are set to “0000000”.
15. The MODE pin is pulled low by an internal resistor.
Parameter Symbol Min Typ Max Unit
Master Clock Characteristics
Master Clock Frequency Internal Gate Oscillator (Note 10) MCLK 2.5 4.096 20 MHz
Master Clock Duty Cycle 40 - 60 %
CPUCLK Duty Cycle (Note 11 and 12) 40 60 %
Filter Characteristics
Phase Compensation Range (Voltage Channel, 60 Hz) -2.8 - +2.8 °
Input Sampling Rate DCLK = MCLK/K - DCLK/8 - Hz
Digital Filter Output Word Rate (Both Channels) OWR - DCLK/1024 - Hz
High-pass Filter Corner Frequency -3 dB - 0.5 - Hz
Full Scale Calibration Range (
Referred to Input) (Note 13) FSCR 25 - 100 %F.S.
Channel-to-channel Time-shift Error (Note 14) 1.0 µs
Input/Output Characteristics
High-level Input Voltage
All Pins Except XIN and SCLK and RESET
XIN
SCLK and RESET
V
IH
0.6 VD+
(VD+) - 0.5
0.8VD+
-
-
-
-
-
-
V
V
V
Low-level Input Voltage (VD = 5 V)
All Pins Except XIN and SCLK and RESET
XIN
SCLK and RESET
V
IL
-
-
-
-
-
-
0.8
1.5
0.2VD+
V
V
V
Low-level Input Voltage (VD = 3.3 V)
All Pins Except XIN and SCLK and RESET
XIN
SCLK and RESET
V
IL
-
-
-
-
-
-
0.48
0.3
0.2VD+
V
V
V
High-level Output Voltage I
out
= +5 mA V
OH
(VD+) - 1.0 - - V
Low-level Output Voltage I
out
= -5 mA V
OL
--0.4V
Input Leakage Current (Note 15) I
in
-±1±10µA
3-state Leakage Current I
OZ
--±10µA
Digital Output Pin Capacitance C
out
-5-pF
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P44

CS5461A-ISZR

Mfr. #:
Buy CS5461A-ISZR
Manufacturer:
Cirrus Logic
Description:
Current & Power Monitors & Regulators IC Sngl-Phs BiDirect PWR/Energy
Lifecycle:
New from this manufacturer.
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