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CS5461A-ISZR

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P44
CS5461A
DS661F3 25
5.14.6 Calibration
The CS5461A can perform system calibrations. Proper input signals must be applied to the current and voltage
channel before performing a designated calibration.
CAL[4:0]* Designates calibration to be performed
01001 = Current channel DC offset
01010 = Current channel DC gain
01101 = Current channel AC offset
01110 = Current channel AC gain
10001 = Voltage channel DC offset
10010 = Voltage channel DC gain
10101 = Voltage channel AC offset
10110 = Voltage channel AC gain
11001 = Current and Voltage channel DC offset
11010 = Current and Voltage channel DC gain
11101 = Current and Voltage channel AC offset
11110 = Current and Voltage channel AC gain
*Values for CAL[4:0] not specified should not be used.
B7 B6 B5 B4 B3 B2 B1 B0
1 1 0 CAL4 CAL3 CAL2 CAL1 CAL0
CS5461A
26 DS661F3
6. REGISTER DESCRIPTION
1. “Default” => bit status after power-on or reset
2. Any bit not labeled is Reserved. A zero should always be used when writing to one of these bits.
6.1 Configuration Register
Address: 0
Default = 0x000001
PC[6:0] Phase compensation. A 2’s complement number which sets a delay in the voltage channel rel-
ative to the current channel. When MCLK = 4.096 MHz and K = 1, the phase adjustment range
is approximately 2.8 degrees with each step approximately 0.04 degrees (assuming a power
line frequency of 60 Hz). If (MCLK/K) is not 4.096 MHz, the values for the range and step size
should be scaled by the factor 4.096 MHz/ (MCLK/K). Default setting is 0000000 = 0.0215 de-
gree phase delay at 60 Hz (when MCLK = 4.096 MHz).
Igain Sets the gain of the current PGA.
0 = Gain is 10x (default)
1 = Gain is 50x
EWA Allows the E1
and E2 pins to be configured as open-collector output pins.
0 = Normal outputs (default)
1 = Only the pull-down device of the E1
and E2 pins are active
IMODE, IINV Interrupt configuration bits. Select the desired pin behavior for indication of an interrupt.
00 = Active-low level (default)
01 = Active-high level
10 = High-to-low pulse
11 = Low-to-high pulse
EPP Allows the E1
and E2 pins to be controlled by the EOP and EDP bits.
0 = Normal operation of the E1
and E2 pins. (default)
1 = EOP and EDP bits defines the E1
and E2 pins.
EOP EOP defines the value of the E1
pin when EPP = 1.
0 = Logic level low (default)
EDP EDP defines the value of the E2
pin when EPP = 1.
0 = Logic level low (default)
ALT Alternate pulse format, E1
and E2 becomes active low alternating pulses with an output fre-
quency proportional to the active power.
0 = Normal (default), Mechanical Counter or Stepper Motor Format
1 = Alternate Pulse Format, also MECH = 1
VHPF (IHPF) Enables the high-pass filter on the voltage (current) channel.
0 = High-pass filter disabled (default)
1 = High-pass filter enabled
23 22 21 20 19 18 17 16
PC6 PC5 PC4 PC3 PC2 PC1 PC0
Igain
15 14 13 12 11 10 9 8
EWA IMODE IINV EPP EOP EDP
76543210
ALT VHPF IHPF iCPU K3 K2 K1 K0
CS5461A
DS661F3 27
iCPU Inverts the CPUCLK clock. In order to reduce the level of noise present when analog signals
are sampled, the logic driven by CPUCLK should not be active during the sample edge.
0 = Normal operation (default)
1 = Minimize noise when CPUCLK is driving rising-edge logic
K[3:0] Clock divider. A 4-bit binary number used to divide the value of MCLK to generate the internal
clock DCLK. The internal clock frequency is DCLK = MCLK/K. The value of K can range be-
tween 1 and 16. A value of “0000” will set K to 16 (not zero). K = 1 at reset.
6.2 Current and Voltage DC Offset Register ( I
DCoff
,V
DCoff
)
Address: 1 (Current DC Offset); 3 (Voltage DC Offset)
Default = 0x000000
The DC Offset registers (I
DCoff
,V
DCoff
) are initialized to 0.0 on reset. When DC Offset calibration is performed, the
register is updated with the DC offset measured over a computation cycle. DRDY will be asserted at the end of
the calibration. This register may be read and stored for future system offset compensation. The value is repre-
sented in two's complement notation and in the range of -1.0 I
DCoff
, V
DCoff
1.0, with the binary point to the
right of the MSB.
6.3 Current and Voltage Gain Register ( I
gn
,V
gn
)
Address: 2 (Current Gain); 4 (Voltage Gain)
Default = 0x400000 = 1.000
The gain registers (I
gn
,V
gn
)
are initialized to 1.0 on reset. When either a AC or DC Gain calibration is performed,
the register is updated with the gain measured over a computation cycle. DRDY will be asserted at the end of
the calibration. This register may be read and stored for future system gain compensation. The value is in the
range 0.0 I
gn
,V
gn
< 3.9999, with the binary point to the right of the second MSB.
6.4 Cycle Count Register
Address: 5
Default = 0x000FA0 = 4000
Cycle Count, denoted as N, determines the length of one computation cycle. During continuous conversions,
the computation cycle frequency is (MCLK/K)/(1024N). A one second computational cycle period occurs when
MCLK = 4.096 MHz, K = 1, and N = 4000.
MSB LSB
-(2
0
)2
-1
2
-2
2
-3
2
-4
2
-5
2
-6
2
-7
.....
2
-17
2
-18
2
-19
2
-20
2
-21
2
-22
2
-23
MSB LSB
2
1
2
0
2
-1
2
-2
2
-3
2
-4
2
-5
2
-6
.....
2
-16
2
-17
2
-18
2
-19
2
-20
2
-21
2
-22
MSB LSB
2
23
2
22
2
21
2
20
2
19
2
18
2
17
2
16
.....
2
6
2
5
2
4
2
3
2
2
2
1
2
0
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P44

CS5461A-ISZR

Mfr. #:
Buy CS5461A-ISZR
Manufacturer:
Cirrus Logic
Description:
Current & Power Monitors & Regulators IC Sngl-Phs BiDirect PWR/Energy
Lifecycle:
New from this manufacturer.
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