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CS5461A-ISZR

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P44
CS5461A
DS661F3 31
6.15 Pulsewidth Register ( PW )
Address: 21
Default = 0x000200 = 512 sample periods
PW sets the pulsewidth of E1
and E2 pulses in Alternate Pulse and Mechanical Counter format. The width is a
function of number of sample periods. The default corresponds to a pulsewidth of
512 samples/[(MCLK/K)/1024] = 128 msec with MCLK = 4.096 MHz and K = 1. The value is represented in un-
signed notation.
6.16 E3 Pulse Width Register ( PulseWidth
)
Address: 22
Default = 0x000000 = Hardware-generated pulse width (up to 125 s)
The PulseWidth register sets the pulse width of E3
pulses in units of 1/OWR.
E3
pulse width =
The range of this register is from 1 to 8388607.
6.17 Voltage Sag Duration Register ( VSAG
Duration
)
Address: 23
Default = 0x000000
Voltage Sag Duration (VSAG
Duration
) defines the number of instantaneous voltage measurements utilized to de-
termine a voltage level sag event (VSAG
LEVEL
). Setting this register to zero will disable Voltage Sag-detect. The
value is represented in unsigned notation.
6.18 Voltage Sag Level Register ( VSAG
Level
)
Address: 24
Default = 0x000000
Voltage Sag Level (VSAG
Level
) defines the voltage level that the magnitude of input samples, averaged over the
sag duration, must fall below in order to register a sag condition. This value is represented in unsigned notation
and in the range of 0 VSAG
Level
1.0, with the binary point to the right of the MSB.
MSB LSB
2
23
2
22
2
21
2
20
2
19
2
18
2
17
2
16
.....
2
6
2
5
2
4
2
3
2
2
2
1
2
0
MSB LSB
0
2
22
2
21
2
20
2
19
2
18
2
17
2
16
.....
2
6
2
5
2
4
2
3
2
2
2
1
2
0
MSB LSB
0
2
22
2
21
2
20
2
19
2
18
2
17
2
16
.....
2
6
2
5
2
4
2
3
2
2
2
1
2
0
PulseWidth
MCLK
K1024
---------------------------------------------
MSB LSB
0
2
-1
2
-2
2
-3
2
-4
2
-5
2
-6
2
-7
.....
2
-17
2
-18
2
-19
2
-20
2
-21
2
-22
2
-23
CS5461A
32 DS661F3
6.19 No Load Threshold Interval Register ( LoadIntv)
Address: 25
Default = 0x000000 = No load threshold feature disabled
LoadMin determines the duration or interval of the no load detection window in units of 1/OWR. The range is
from 1 to 16777215.
6.20 No Load Threshold ( LoadMin )
Address: 27
Default = 0x000000 = No load threshold feature disabled
LoadMin sets the no load threshold value. LoadMin is a two’s complement value in the range of
-1.0 LoadMin 1.0 with the binary point to the right of the MSB. Negative values are not allowed.
MSB LSB
2
23
2
22
2
21
2
20
2
19
2
18
2
17
2
16
.....
2
6
2
5
2
4
2
3
2
2
2
1
2
0
MSB LSB
-(2
0
)2
-1
2
-2
2
-3
2
-4
2
-5
2
-6
2
-7
.....
2
-17
2
-18
2
-19
2
-20
2
-21
2
-22
2
-23
CS5461A
DS661F3 33
6.21 Control Register
Register Address: 28
Default = 0x000000
FAC Determines if anti-creep is enabled for pulse output E3.
0 = Disable anti-creep (default)
1 = Enabled anti-creep
EAC Determines if anti-creep is enabled for pulse output E1 and/or E2.
0 = Disable anti-creep (default)
1 = Enabled anti-creep
STOP Terminates the auto-boot sequence.
0 = Normal (default)
1 = Stop sequence
MECH Mechanical Counter Format, E1
or E2 becomes active low pulses with an output frequency pro-
portional to the active power
0 = Normal (default) or Stepper Motor Format
1 = Mechanical Counter Format, also ALT = 0
INTOD Converts INT output pin to an open drain output.
0 = Normal (default)
1 = Open drain
NOCPU Saves power by disabling the CPUCLK pin.
0 = Normal (default)
1 = Disables CPUCLK
NOOSC Saves power by disabling the crystal oscillator.
0 = Normal (default)
1 = Oscillator circuit disabled
STEP Stepper Motor Format, E1
and E2 becomes active low pulses with an output frequency propor-
tional to the active power
0 = Normal Format (default)
1 = Stepper Motor Format, also MECH = 0 and ALT = 0
6.22 Temperature Gain Register ( T
Gain
)
Address: 29
Default = 0x2F02C3 = 23.5073471
Sets the temperature channel gain. Temperature gain (T
Gain
) is utilized to convert from one temperature scale to an-
other. The Celsius scale (
o
C) is the default. Values are represented in unsigned notation and in the range of
0 T
Gain
128, with the binary point to the right of the seventh MSB.
23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8
FAC EAC STOP
76543210
MECH INTOD NOCPU NOOSC STEP
MSB LSB
2
6
2
5
2
4
2
3
2
2
2
1
2
0
2
-1
.....
2
-11
2
-12
2
-13
2
-14
2
-15
2
-16
2
-17
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P44

CS5461A-ISZR

Mfr. #:
Buy CS5461A-ISZR
Manufacturer:
Cirrus Logic
Description:
Current & Power Monitors & Regulators IC Sngl-Phs BiDirect PWR/Energy
Lifecycle:
New from this manufacturer.
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