NCV7462
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16
ELECTRICAL CHARACTERISTICS
(−40°C T
J
150°C, 6 V Vs 18 V, unless otherwise specified)
Table 20. SPI TIMING
Symbol Parameter Test Condition Min Typ Max Unit
tCSN_SCLK
First SPI clock edge after
CSN active
(Note 3) 100 ns
tCSN_SDO
SDO output stable after
CSN active
(Note 3) 80 ns
tCSN_High
Inter−frame space (CSN
inactive)
(Note 3) 14
ms
tSCLK_High
Duration of SPI clock High
level
(Note 3) 250 ns
tSCLK_Low
Duration of SPI clock Low
level
(Note 3) 250 ns
tSCLK_per SPI clock period (Note 3) 1
ms
tSDI_set
Setup time of SDI input
towards SPI clock
(Note 3) 100 ns
tSDI_hold
Hold time of SDI input
towards SPI clock
(Note 3) 100 ns
tSCLK_SDO
SDO output stable after
SPI clock falling edge
(Note 3) 250 ns
3. Values based on design and characterization, not tested in production.
CSN
SCLK
SDO
t
CSN_SDO
t
SCLK_per
t
SCLK_Low
t
SCLK_High
t
CSN_SCLK
t
SDI_set
t
SDI_hold
t
SCLK_SDO
t
CSN_High
SDI
Figure 5. SPI Timing Parameters
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ELECTRICAL CHARACTERISTICS
(−40°C T
J
150°C, 6 V Vs 18 V, unless otherwise specified)
Table 21. WINDOW WATCHDOG
Symbol Parameter Test Condition Min Typ Max Unit
Twd_acc Watchdog timing accuracy −25 25 %
T_wd_TO
Timeout watchdog period;
(watchdog is in the timeout
mode after NRES release)
48.75 65 81.25 ms
T_wd_CW
Window watchdog closed
window
SPI WD_PER.x = 00 6
ms
SPI WD_PER.x = 01 24
SPI WD_PER.x = 10 60
SPI WD_PER.x = 11 120
T_wd_OW
Window watchdog open
window
SPI WD_PER.x = 00 10
ms
SPI WD_PER.x = 01 40
SPI WD_PER.x = 10 100
SPI WD_PER.x = 11 200
T_wd_trig
Window watchdog trigger
period via SPI
(the safe trigger area)
SPI WD_PER.x = 00 7.5 9.75 12
ms
SPI WD_PER.x = 01 30 39 48
SPI WD_PER.x = 10 75 97.5 120
SPI WD_PER.x = 11 150 195 240
T_wd_33_TO
WD_STATUS.0 bit
threshold of timeout length
(in timeout mode)
31.5 %
T_wd_66_TO
WD_STATUS.1 bit
threshold of timeout length
(in timeout mode)
63 %
T_wd_33_OW
WD_STATUS.0 bit
threshold of open window
length (in open window
mode)
SPI WD_PER.x = 00 26.5
%
SPI WD_PER.x = 01 32
SPI WD_PER.x = 10 33.3
SPI WD_PER.x = 11 33.3
T_wd_66_OW
WD_STATUS.1 bit
threshold of open window
length (in open window
mode)
SPI WD_PER.x = 00 63
%
SPI WD_PER.x = 01 76.8
SPI WD_PER.x = 10 66.6
SPI WD_PER.x = 11 66.6
NCV7462
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18
ELECTRICAL CHARACTERISTICS
(−40°C T
J
150°C, 5 V Vs 28 V, Normal mode, unless otherwise specified); the following bus loads are considered: L1 = 1 k W / 1 nF;
L2 = 660 W / 6.8 nF; L3 = 500 W / 10 nF.
Table 22. LIN TRANSMITTER DC CHARACTERISTICS
Symbol Parameter Test condition Min Typ Max Unit
VLin_dom_LoSup
LIN dominant
output voltage
TxDL = low; VS = 7.3 V, L1 1.2 V
VLin_dom_HiSup
LIN dominant
output voltage
TxDL = low; VS = 18 V, L1 2 V
VLin_rec
LIN recessive
output voltage
TxDL = high
I(LIN) = 0 mA
VS − 1.2 V
ILIN_lim
LIN short circuit
current limitation
V(LIN) = 18 V 40 200 mA
Rslave_LIN
Internal pull−up
resistance
20 33 47
kW
Table 23. LIN RECEIVER DC CHARACTERISTICS
Symbol Parameter Test condition Min Typ Max Unit
Vbus_dom_LIN Bus voltage for
dominant state
0.4 VS
Vbus_rec_LIN Bus voltage for
recessive state
0.6 VS
Vrec_dom_LIN Receiver threshold LIN bus recessive −> dominant 0.4 0.5 VS
Vrec_rec_LIN Receiver threshold LIN bus dominant −> recessive 0.5 0.6 VS
Vrec_cnt_LIN
Receiver threshold
centre voltage
(Vrec_rec_LIN + Vrec_dom_LIN)
/ 2
0.475 0.525 VS
Vrec_hys_LIN Receiver hysteresis (Vrec_rec_LIN − Vrec_dom_LIN) 0.05 0.175 VS
Vrec_rec_slp_LIN
LIN wake receiver
threshold
Sleep or standby mode VS − 3.3 VS − 1.1 V
ILIN_off_dom
LIN output current,
bus in dominant
state
Normal mode, driver off;
VS = 12 V; V(LIN) = 0 V
−1 mA
ILIN_off_dom_slp
LIN output current,
bus in dominant
state
Sleep mode, driver off;
VS = 12 V; V(LIN) = 0 V
−20 −15 −2
mA
ILIN_off_rec
LIN output current,
bus in recessive
state
Driver off;
VS < 18 V; VS < V(LIN) < 18 V
20
mA
ILIN_no_GND
LIN current with
missing GND
VS = GND = 12 V;
0 < V(LIN) < 18 V
−1 1 mA
ILIN_no_VS
LIN current with
missing VS
VS = GND = 0 V;
0 < V(LIN) < 18 V
100
mA

NCV7462DQ0R2G

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
CAN Interface IC CAN LIN 250MA LDO SBC
Lifecycle:
New from this manufacturer.
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