NCV7462
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19
ELECTRICAL CHARACTERISTICS
(−40°C ≤ T
J
≤ 150°C, 5 V ≤ Vs ≤ 28 V, Normal Mode, unless otherwise specified); the following bus loads are considered: L1 = 1 k W / 1 nF;
L2 = 660 W / 6.8 nF; L3 = 500 W / 10 nF.
Table 24. LIN TRANSMITTER DYNAMIC CHARACTERISTICS
Symbol Parameter Test condition Min Typ Max Unit
D1
Duty Cycle 1 =
tBUS_REC(min) /
(2 x TBit)
THREC(max) = 0.744 x VS
THDOM(max) = 0.581 x VS
TBIT = 50 ms
VS = 7 V to 18 V
0.396 0.5 −
D2
Duty Cycle 2 =
tBUS_REC(max) /
(2 x TBit)
THREC(min) = 0.422 x VS
THDOM(min) = 0.284 x VS
TBIT = 50 ms
VS = 7.6 V to 18 V
0.5 0.581 −
D3
Duty Cycle 3 =
tBUS_REC(min) /
(2 x TBit)
THREC(max) = 0.788 x VS
THDOM(max) = 0.616 x VS
TBIT = 96 ms
VS = 7 V to 18 V
0.417 0.5 −
D4
Duty Cycle 4 =
tBUS_REC(max) /
(2 x TBit)
THREC(min) = 0.389 x VS
THDOM(min) = 0.251 x VS
TBIT = 96 ms
VS = 7.6 V to 18 V
0.5 0.59 −
T_fall_LIN LIN falling edge
VS = 12 V; L1, L2;
Normal slope mode
22.5
ms
T_rise_LIN LIN rising edge
VS = 12 V; L1, L2;
Normal slope mode
22.5
ms
T_sym_LIN LIN slope symmetry
VS = 12 V; L1, L2;
Normal slope mode
−4 0 4
ms
T_fall_norm_LIN LIN falling edge
VS = 12 V; L3;
Normal slope mode
27
ms
T_rise_norm_LIN LIN rising edge
VS = 12 V; L3;
Normal slope mode
27
ms
T_sym_norm_LIN LIN slope symmetry
VS = 12 V; L3;
Normal slope mode
−5 0 5
ms
T_fall_low_LIN LIN falling edge
VS = 12 V; L3;
Low slope mode
62
ms
T_rise_low_LIN LIN rising edge
VS = 12 V; L3;
Low slope mode
62
ms
T_TxDL_timeout
TxDL dominant
time−out
Selected by SPI bits
TxDL_TO
SPI setting ”00” 27 55 70
ms
SPI setting ”01” 6 13 20
SPI setting ”1X” disabled
C_LIN
Capacitance of the
LIN pin
Guaranteed by design;
not tested in production
15 25 pF
