NCV7462
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CAN Transceiver Supply VCC_CAN
The on−chip CAN transceiver block uses two supply
paths:
• From the VCC_CAN supply input: in the normal mode,
when the transceiver is ready for
transmission/reception.
• From the VS supply through internal pre−regulators −
in standby and sleep modes, the transceiver monitors
bus for remote wakeups. The VCC_CAN supply is not
used.
For correct CAN transceiver function in the normal mode,
the VCC_CAN pin must be decoupled with an external
capacitor to ground.
In the normal operating mode, VCC_CAN supply input is
monitored with an under−voltage comparator with level
Vfail_VCAN (typ. 4.3 V). The output of the under−voltage
detector can be read through SPI status bit “VCAN_UV”.
This bit is a direct read−out (without latching) of the
comparator’s output. When the CAN transceiver is enabled,
a VCC_CAN under−voltage is additionally latched in the
SPI status bit “VCAN_FAIL” for subsequent diagnostics.
CAN transceiver functionality is disabled during
VCC_CAN under−voltage.
Communication Transceivers
LIN Transceiver
The NCV7462 on−chip LIN transceiver is an interface
between a physical LIN bus and the LIN protocol controller.
It is compatible to LIN2.x and J2602 specifications.
Unlike the CAN transceiver, the LIN is supplied solely
from the VS pin and its state control is therefore simpler:
• In the normal mode of the device, LIN transceiver
transmits dominant or recessive symbols on the LIN
bus based on the logical level on TxDL pin. The signal
received from the bus is indicated on RxDL pin. Both
logical pins are referred to the VR1 supply. A resistive
pull−up path of typ. 30 kW is internally connected
between LIN and VS. LIN pin remains recessive
regardless the TxDL pin state during VS under−voltage.
See par “VS Over− and Under−Voltage” for details.
• In the standby and sleep modes of the device, the LIN
transceiver is in its wakeup detection state. Logical
level on TxDL is ignored and pin RxDL is kept high
until it’s used as an interrupt request signal. A LIN bus
wakeup corresponds to a dominant symbol at least
T_LIN_wake long (typ. 90 ms) followed by a rising
edge (i.e. transition to recessive) − see Figure 9. In this
way, false wakeups due to permanent LIN dominant
failures are avoided. Only a pull−up current of typ.
15 mA is connected between VS and LIN instead of the
30 kW pull−up path. The LIN wakeup detection is by
default active in the standby and sleep modes and can
be disabled via SPI control registers.
The LIN transceiver features SPI−configurable TxDL
dominant time−out timer. This circuit, if enabled, prevents
the bus lines being driven to a permanent dominant state
(blocking all network communication) if pin TxDL is forced
permanently low by a hardware and/or software application
failure. The timer is triggered by a negative edge on pin
TxDL. If the duration of the low−level on pin TxDL exceeds
the internal timer value T_TxDL_timeout, the transmitter is
disabled, driving the bus into a recessive state and the event
is latched in the SPI status bit “TO_TxDL”. The
transmission is de−blocked when “TO_TxDL” bit is reset by
the corresponding register “read and clear”.
The LIN transceiver provides two LIN slope control
modes, configured by SPI bit “LIN_SLOPE”.
In normal slope mode the transceiver can transmit and
receive data via LIN bus with speed up to 20 kBaud
according LIN2.x specification. This mode is used by
default.
In low slope mode the slew rate of the signal on the LIN
bus is reduced (rising and falling edges of the LIN bus signal
are longer). This further reduces the EMC emission. As a
consequence the maximum speed on the LIN bus is reduced
to 10 kBaud. This mode is suited for applications where the
communication speed is not critical. The low slope mode
can be configured by setting SPI bit “LIN_SLOPE”.
CAN Transceiver
NCV7462 contains a high−speed CAN transceiver
compliant with ISO11898−2 and ISO11898−5. It consists of
the following sub−blocks: transmitter, receiver, wakeup
detector, and common−mode stabilization pin VSPLIT
CAN transceiver control in the normal mode
of the device
is shown in Table 33. By default, the CAN transceiver is
ready to provide the full−speed interface between the bus
and a CAN controller connected on pins RxDC (received
data) and TxDC (data to transmit). Through two dedicated
SPI control bits, the CAN transceiver can be fully disabled
or configured to “listen−only” functionality (RxDC pin
continues to signal the received data while the logical level
on TxDC is ignored and the transmitter remains in
recessive).
The bus common mode can be additionally stabilized by
using a split termination with the central tap connected to the
VSPLIT pin. The transceiver and the VSPLIT are supplied
from VCC_CAN supply input. In order to prevent a faulty
node from blocking the bus traffic, the maximum length of
the transmitted dominant symbol is limited by a time−out
counter to t_TxDC_timeout (typ. 650 ms). In case the TxDC
Low signal exceeds the timeout value, the transmitter
returns automatically to recessive and the event is latched in
the SPI bit “TO_TxDC”. The transmission is again
de−blocked when “TO_TxDC” bit is reset by the
corresponding register “read and clear”.
When the CAN transceiver is enabled in the normal
operating mode, an under−voltage of VCC_CAN
automatically blocks transmission and reception (recessive
sent to the bus and RxDC remains High regardless the real
CAN bus state). When the VCC_CAN returns above the
