NCV7462
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40
VS in range
Normal mode
Standby mode with cyclic sense
Sleep mode with cyclic sense
HS, LS outputs: as per SPI
LIN transmitter: as per SPI
VS Under−Voltage
VS_UV bit set
HS outputs: off
LSx: off if LS_OVUV bit=0; unaffected otherwise
LIN transmitter: off
VS Over−Voltage
VS_OV bit set
HS outputs: off
LSx: off if LS_OVUV bit=0; unaffected otherwise
LIN transmitter: as per SPI
VS<VS_UV VS>VS_OV
VS<VS_OV
AND
(VS_OV bit read and cleared
OR
VS_LOCKOUT_DIS bit=1)
VS>VS_UV
AND
(VS_UV bit read and cleared
OR
VS_LOCKOUT_DIS bit=1)
Figure 17. Under− and Over−voltage on VS Supply
Reset Signal NRES
NRES is an open−drain output with an internal pull−up
resistor connected to VR1. It signals reset to the MCU as a
consequence of several specific events:
• VR1 under−voltage (including VS power−up)
• Watchdog failure
• Thermal shutdown level 2
• Wakeup (in case the wakeup is accompanied by reset −
see Table 35)
• (Forced) Sleep mode
The low−level pulse on NRES pins always extends
T_NRES (typ. 2 ms) beyond the reset event − e.g. a
watchdog failure causes a 2 ms NRES low pulse; a VR1
under−voltage causes NRES pulse extending 2 ms beyond
the under−voltage disappearance.
After NRES pulse, which was caused by VR1
under−voltage or watchdog failure, all outputs (OUT1−4,
LS1/2 and VR2) are inactive. SPI registers content is
preserved. Outputs follow relevant SPI register settings after
the correct watchdog setting again.
LIN and CAN transmission is blocked during NRES
pulse. CAN and LIN receivers are enabled if NRES pulse
was caused by VR1 undervoltage, disabled otherwise. A
recessive−to−dominant edge on TxDL pin after NRES pulse
is required to start transmission to LIN bus.
Interrupt Signal
An interrupt request is used in the standby mode to
indicate some of the wakeup events to the MCU − see section
“Wake−up Events”. Interrupt is signaled through RxDL pin
by pulling it Low for typically 125 ms. Beside the 125 ms
Low pulse, RxDL remains High throughout the standby
mode.
During normal mode, RxDL assumes its normal function
(LIN received data).
Operational Amplifiers
Two operating amplifiers are provided for, mainly, current
sensing (see Figure 3). The operating amplifiers are on (i.e.
biased) in the normal mode. They are powered−down in all
other modes.
The input voltage common mode covers the range from
−0.2 V to 3 V. The rail−to−rail (VS) output voltage allows
using them together with an external pass element as
additional voltage regulator.
Fail−Safe (FSO) Signal
A fail−safe signal is internally generated reflecting some
critical system failures and events. By default, the signal is
connected to the OUT3 output and over−rules the OUT3 SPI
settings − active FSO signal switches OUT3 on, inactive
FSO signal switches OUT3 off. In case the SPI bit
“FSO_DIS” is set, OUT3 acts as a general−purpose
high−side driver identically to OUT1, 2 and 4. FSO remains
then only an internal signal not visible to the application.
FSO internal signal is active in the following cases:
• During the Init phase:
♦ VR1 short: FSO is active when VR1 is below its
failure level (Vfail_VR1) for more than Tshort_VR1
(typ. 4 ms) during VR1 regulator startup and VS is
above VS_UV threshold (typ. 5.5 V).
• In the normal and standby modes:
♦ VR1 under−voltage: FSO is active when VR1 is
below its reset level (VR1_RES).
♦ Watchdog: FSO is immediately activated in case of
failed watchdog trigger. It is deactivated only when
the watchdog is correctly triggered again.
♦ Thermal shutdown: FSO is active when the junction
temperature is above the second shutdown threshold
(Tjsd2).
• In the forced sleep modes: FSO is active if the forced
sleep mode was entered because of a failure condition,
like non−starting VR1, repeated thermal shutdown or
repeated watchdog failures. If the sleep mode is entered
by a correct SPI mode−transition request, FSO remains
inactive.
