NCN6004A
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10
POWER SUPPLY SECTION General test conditions, unless otherwise specified: Operating temperature: −25°C < T
A
< +85°C,
V
CC
= +3.0 V, CRD_VCC_A = CRD_VCC_B = +5.0 V.
Rating Symbol Pin Min Typ Max Unit
I
out
= 2 x 65 mA (both external cards running simultaneously)
@ 3.0 V < V
CC
< 5.5 V
CRD_VCC 29, 32
4.6 5.4
V
I
out
= 2 x 55 mA per pin (both external cards running)
V
out
defined @ CRD_VCC = 3.0 V @ 3.0 V < V
CC
< 5.5 V
CRD_VCC 29, 32
2.7 3.3
V
I
out
= 2 x 35 mA per pin (both external cards running)
V
out
defined @ CRD_VCC = 1.80 V @ 3.0 V < V
CC
< 5.5 V
CRD_VCC 29, 32
1.65 1.95
V
Output Card Supply Voltage Ripple (per CRD_VCC outputs) @ :
L
out
= 22 mH, L
ESR
< 2.0 W, C
out
= 10 mF per CRD_VCC (Note 5)
I
out
= 35 mA, V
out
= 1.80 V
I
out
= 55 mA, V
out
= 3.0 V
I
out
= 65 mA, V
out
= 5.0 V
V
ORA
V
ORB
29
32
50
50
50
mV
DC/DC Dynamic Inductor Peak Current @ V
bat
= 5.0 V, L
out
= 22 mH,
C
out
= 10 mF
CRD_VCC = 1.8 V
CRD_VCC = 3.0 V
CRD_VCC = 5.0 V
I
ccov
29, 32
200
280
430
mA
Standby Supply Current Conditions (Note 5):
ANLG_VCC = PWR_VCC = 3.0 V
PWR_ON = H, STATUS = H, CS = H
Card A and Card B CLOCK_IN = H, I/O = H, RESET = H
All Logic Inputs = H, Temperature range = 0°C to +50°C
ANLG_VCC = PWR_VCC = 5.0 V
Temperature range –25°C to +85°C
All other test conditions identical
ANLG_VCC = PWR_VCC = 1.8 V
Temperature range –25°C to +50°C
All other test conditions identical
Note: This parameter is guaranteed by design, not production tested.
I
DD
42, 28,
33
20
50
5.0
mA
Operating Supply Current
ANLG_VCC = PWR_VCC = 5.5 V
@ CRD_VCC_A/B = 5.0 V
@ CRD_VCC_ A/B = 3.0 V
@ CRD_VCC_ A/B = 1.85 V
ANLG_VCC = PWR_VCC = 3.3 V
@ CRD_VCC_A/B = 5.0 V
@ CRD_VCC_ A/B = 3.0 V
@ CRD_VCC_ A/B = 1.85 V
PWR_ON = H, CS = H, CLK_A = CLK_B = Low, all card pins unloaded
I
DDop
42, 28,
33
0.7
0.7
0.7
0.2
0.2
0.2
mA
V
bat
Under Voltage Detection Positive Going Slope
V
bat
Under Voltage Detection Negative Going Slope
V
bat
Under Voltage Detection Hysteresis
Note: The voltage present in pins 28 and 33 must be equal to or
Note: lower than the voltage present in pin 42.
V
batLH
V
batLL
V
batHY
42 2.1
2.0
100
2.7
2.6
V
V
mV
Output Continuous Current Card A or Card B (both cards can be
operating simultaneously) @ 3.0 < V
CC
< 5.5 V
Output Voltage = 1.85 V
Output Voltage = 3.0 V
Output Voltage = 5.0 V
I
ccp
31, 42
35
55
65
mA
Output Over Current Limit (A or B)
V
bat
= 3.3 V, CRD_VCC = 1.8 V, 3.0 V or 5.0 V
V
bat
= 5.0 V, CRD_VCC = 1.8 V, 3.0 V or 5.0 V
I
ccov
31, 42
100
150
mA
Output Over Current Time Out Per Card I
tdoff
31, 42 4.0 ms
Output Card Supply Turn On Time @ L
out
= 22 mF, C
out
= 10 mF Ceramic.
V
CC
= 2.7 V, CRD_VCC = 5.0 V (A or B)
V
CCTON
31, 42
500
ms
5. Assuming ANLG_VCC and PWR_VCC pins are connected to the same power supply.
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11
POWER SUPPLY SECTION General test conditions, unless otherwise specified: Operating temperature: −25°C < T
A
< +85°C,
V
CC
= +3.0 V, CRD_VCC_A = CRD_VCC_B = +5.0 V. (continued)
Rating UnitMaxTypMinPinSymbol
Output Card Supply Shut Off Time @
C
out
= 10 mF, ceramic.
V
CC
= 2.7 V, CRD_VCC = 5.0 V, V
CCOFF
< 0.4 V (A or B)
V
CCTOFF
31, 42
100 250
ms
DC/DC Converter Operating Frequency (A or B) F
SW
31, 42 600 kHz
5. Assuming ANLG_VCC and PWR_VCC pins are connected to the same power supply.
DIGITAL INPUT/OUTPUT SECTION
2.70 < V
CC
< 5.50 V, Normal Operating Mode (−25°C to +85°C ambient temperature, unless otherwise noted)
Rating Symbol Pin Min Typ Max Unit
A0, A1, A2, A3, CARD_SEL, PWR_ON, PGM, CS, MUX_MODE,
EN_RPU, RESET_A, RESET_B, C4_A, C8_A, C4_B, C8_B
High Level Input Voltage
Low Level Input Voltage
Input Capacitance
V
IH
V
IL
C
in
1, 2, 3,
4, 5, 6,
7, 8,
44, 45,
10, 18,
11, 12,
16, 17
0.7 * V
bat
V
bat
0.3 * V
bat
10
V
V
pF
STATUS, INT
Output High Voltage @ I
OH
= −10 mA
Output Low Voltage @ I
OH
= 200 mA
V
OH
V
OL
46, 47
V
bat
–1.0 V
0.40
V
STATUS, INT
Output Rise Time @ C
out
= 30 pF
Output Fall Time @ C
out
= 30 pF
trsta, trint
tfsta, tfint
5
100
ms
ns
CLOCK_A Asynchronous Input Clock @ DC = 50% "1% F
CLKINA
13 40 MHz
CLOCK_B Asynchronous Input Clock @ DC = 50% "1% F
CLKINB
15 40 MHz
I/O_A, I/O_B, both directions @ C
out
= 30 pF
I/O Rise Time
I/O Fall Time
t
rioA
, t
rioB
t
fioA
, t
fioB
9, 19 0.8
0.8
ms
STATUS Pull Up Resistance R
STA
46 35 50
kW
INT Pull Up Resistance R
INT
47 35 50
kW
I/O_A Pull Up Resistance R
IOA
9 14 20 35
kW
I/O_B Pull Up Resistance R
IOB
19 14 20 35
kW
RESET_A Pull Up Resistance R
RSTA
10 60 100
kW
RESET_B Pull Up Resistance R
RSTB
18 60 100
kW
C4_A Pull Up Resistance R
C4A
11 60 100
kW
C8_A Pull Up Resistance R
C8A
12 60 100
kW
C4_B Pull Up Resistance R
C4B
17 60 100
kW
C8_B Pull Up Resistance R
C8B
16 60 100
kW
CS Pull Up Resistance R
CS
7 60 100
kW
CRD_DET_A and CRD_DET_B Pull Up Resistance R
DETA
R
DETB
20
41
500
500
kW
kW
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12
CARD INTERFACE SECTION @ 2.70 < V
CC
< 5.50 V, Normal Operating Mode (−25°C to +85°C ambient temperature, unless
otherwise noted) CRD_VCC_A = CRD_VCC_B = 1.8 V or 3.0 V or 5.0 V
Rating Symbol Pin Min Typ Max Unit
CRD_RST_A, CRD_RST_B Output Voltage
Output RST High Level @ Irst = −200 mA
Output RST Low Level @ Irst = 200 mA
CRD_RST_A, CRD_RST_B Rise and Fall time
RST Rise Time @ C
out
= 30 pF
RST Fall Time @ C
out
= 30 pF
V
OH
V
OL
trrst
tfrst
23, 38
23, 38
23, 38
23, 38
CRD_VCC−0.5
0
CRD_VCC
0.4
100
100
V
V
ns
ns
CRD_CLK_A, CRD_CLK_B Output Clock
Output Operating Clock Card A and Card B
Output Operating Clock DC, Card A and Card B
(Input DC = 50%, "1%)
Note: This parameter is guaranteed by design, functionality 100%
tested at production.
Output Operating Clock Rise Time SLOW Mode
Card A and Card B
Output Operating Clock Fall Time SLOW Mode
Card A and Card B
Output Operating Clock Rise Time FAST Mode
Card A and Card B
Output Operating Clock Fall Time FAST Mode
Card A and Card B
Output Clock High Level, Card A and Card B, @ Iclk = −200 mA
Output Clock Low Level, Card A and Card B, @ Iclkc = 200 mA
F
clkA
, F
clkB
trclka, trclkb
tfclka, tfclkb
trclka, trclkb
tfclka, tfclkb
V
OH
V
OL
30, 31
45
CRD_VCC−0.5
0
20
55
16
16
4
4
CRD_VCC
0.4
MHz
%
ns
ns
ns
ns
V
V
CRD_IO_A, CRD_IO_B Data Transfer
Data Transfer Frequency, Card A and Card B
Data Rise Time, Card A and Card B, @ C
out
= 30 pF
Data Fall Time, Card A and Card B, @ C
out
= 30 pF
Data Output High Level, Card A and Card B @ Icrd_io = −20 mA
Data Output Low Level, Card A and Card B @ Icrd_io = 20 mA
F
IOA
, F
IOB
t
rioa,
t
riob
t
fioa,
t
fiob
V
OH
V
OL
24, 37
CRD_VCC−0.5
0
400
0.8
0.8
CRD_VCC
0.4
kHz
ms
ms
V
V
CRD_IO_A and CRD_IO_B Output Voltages
I/O_A = I/O_B = 0, I
OL
= 500 mA
V
OL
24, 37
0.40
V
CRD_C4_A, CRD_C4_B Output Voltages
Output C4 High Level @ Irst = −200 mA
Output C4 Low Level @ Irst = 200 mA
CRD_C4_A, CRD_C4_B Rise and Fall time
C4 Rise Time @ C
out
= 30 pF
C4 Fall Time @ C
out
= 30 pF
V
OH
V
OL
trc
4
tfc
4
22, 39
CRD_VCC−0.5
0
CRD_VCC
0.4
100
100
V
V
ns
ns
CRD_C8_A, CRD_C8_B Output Voltages
Output C4 High Level @ Irst = −200 mA
Output C4 Low Level @ Irst = 200 mA
CRD_C8_A, CRD_C8_B Rise and Fall Time
C8 Rise Time @ C
out
= 30 pF
C8 RST Fall Time @ C
out
= 30 pF
V
OH
V
OL
trc
8
tfc
8
21, 40
CRD_VCC−0.5
0
CRD_VCC
0.4
100
100
V
V
ns
Pull Up resistance, CS = Low, PWR_ON = High
CRD_IO_A
CRD_IO_B
R
OLA
R
OLB
24
37
14
14
20
20
35
35
kW
Card Detection Bias Pull Up Current, Card A or Card B
CRD_DET_A, CRD_DET_B
I
DETA
I
DETB
20
41
15
15
mA
Card Insertion/Extraction Negative Going Input Low Voltage V
ILDETA
V
ILDETB
20
41
0
0
0.30 * V
bat
0.30 * V
bat
V
Card Detection Insertion/Extraction Digital Filtering Delay
CRD_DET_A
CRD_DET_B
t
dcina
t
dcinb
20
41
50
50
ms
CARD_A or CARD_B short circuit current:
CRD_IO, CRD_RST, CRD_C4, CRD_C8
CRD_CLK
(According to ISO and EMV specifications)
Ishort
Ishortclk
15
70
mA

NCN6004AFTBR2

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
I/O Controller Interface IC 2.7V POS/ATM Smart
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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