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NCN6004AFTBR2

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P40
NCN6004A
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4
PIN DESCRIPTION
Pin Symbol Type Description
1 A0 INPUT This pin is combined with CS, A1, A2, A3, CARD_SEL and PGM to program the chip
mode of operation, the CRD_VCC voltage value, and to read the data provided by the
internal STATUS register (Table 1).
2 A1 INPUT This pin is combined with CS, A0, A2, A3, CARD_SEL and PGM to program the chip
mode of operation, the CRD_VCC voltage value, and to read the data provided by the
internal STATUS register (Table 1).
3 A2 INPUT This pin is combined with CS, A0, A1, A3, CARD_SEL and PGM to program the chip
mode of operation, the CRD_VCC voltage value, and to read the data provided by the
internal STATUS register (Table 1).
4 A3 INPUT This pin is combined with CS, A0, A1, A2, CARD_SEL and PGM to program the chip
mode of operation, the CRD_VCC voltage value, and to read the data provided by the
internal STATUS register (Table 1).
5 CARD_SEL INPUT This pin provides logic identification of the Card #A/Card #B external smart card. The
logic signal is set up by the external microcontroller.
CARD_SEL = High → selection of the Smart Card A connected to pins 20, 21, 22, 23, 24,
29 and 30 (respectively CRD_DET_A, CRD_C8_A, CRD_C4_A, CRD_RST_A,
CRD_IO_A, CRD_VCC_A and CRD_CLK_A).
CARD_SEL = Low → selection of the Smart Card B connected to pins 41, 39, 40, 31, 38,
37, and 32 (respectively CRD_DET_B, CRD_C4_B, CRD_C8_B, CRD_CLK_B,
CRD_RST_B, CRD_IO_B, and CRD_VCC_B).
6 PGM DIGITAL INPUT This pin is combined with CS, A0, A1, A2, A3, and CARD_SEL to program the chip mode
of operation and to read the data provided by the internal STATUS register (Figure 4 and
Table 1).
PGM = H→ the NCN6004A is under normal operation and all the data with the external
card can be exchanged using any of the Smart Card A or Smart Card B Lines
PGM = Low → the NCN6004A runs the programming mode and related parameters can
be re programmed according to a given need. In this case, the related card side logic
signals are latched in their previous states and no transaction can occurs.
The programmed states are latched upon the PGM rising slope (Figure 4).
7 CS DIGITAL INPUT This pin provides the Chip Select Function for the NCN6004A device.
CS = High → Pins A0, A1, A2, A3, CARD_SEL, PGM, PWR_ON, RESET_A, RESET_B,
C4_A, C4_B, C8_A, C8_B, I/O_A and I/O_B are disabled, the pre activated CRD_VCC
maintains it’s currently programmed value.
CS = Low → Pins A0, A1, A2, A3, CARD_SEL, PGM, PWR_ON, RESET_A, RESET_B,
C4_A, C4_B, C8_A, C8_B, I/O_A and I/O_B are activated, all the functions being
available.An internal pull up resistor, connected to V
CC
, provides a logic bias when the
external mP is in the high impedance state.
8 PWR_ON DIGITAL INPUT This pin activates or deactivates the DC/DC converter selected by CARD_SEL upon
positive/negative going transient.
PWR_ON = Positive going High → DC/DC Activated
PWR_ON = Negative going L → DC/DC switched Off, no power is applied to the
associated output CRD_VCC pin.
Since uncontrolled action could take place during the rise voltage of the related
CRD_VCC_x output, care must be observed to avoid a PWR_ON negative going
transient during this period of time. To avoid any logical latch up, using a minimum 1.0 ms
delay is recommended prior to power down the related DC/DC converter following a
power up command (Figure 12).
9 I/O_A INPUT/OUTPUT This pin carries the data transmission between an external microcontroller and the
external smart card #A.
A built−in bi−directional level translator adapts the signal flowing between the card and
the MCU. The level translator is enabled when CS = Low. Since a dedicated line is used
to communicate the data between the MPU and the smart card, the user can activate the
two channels simultaneously, assuming the mP provides a pair of I/O lines.
When MUX_MODE = High, this pin provides an access to either card A or B I/O by
means of CARD_SEL selection bit. On the other hand, the internal pull up resistor is
automatically disconnected when MUX_MODE = High, avoiding a current overload on
the I/O line, regardless of the EN_RPU logic level.
This pull up resistor is under the EN_RPU control when MUX_MODE = Low.
NCN6004A
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5
PIN DESCRIPTION (continued)
Pin DescriptionTypeSymbol
10 RESET_A INPUT The signal present on this pin is translated to the RST pin of the external smart card #A. The
CS signal must be Low to validate the RESET function, regardless of the selected card.
Assuming the mP provides two independent lines to control the RESET pins, the
NCN6004A can control two cards simultaneously.
When MUX_MODE = High, this pin provides an access to either card A or B Reset by
means of CARD_SEL selection bit.
The associated pull up resistor is either connected to V
CC
(EN_RPU = H) or
disconnected when EN_RPU = Low.
11 C4_A INPUT This pin controls the card #A C4 contact The signal can be either de−multiplexed, at MPU
level, or is multiplexed with C4_B, depending upon the MUX_MODE logic state.
When MUX_MODE = High, this pin provides an access to either card A or B C4 channel
by means of CARD_SEL selection bit.
The associated pull up resistor is either connected to V
CC
(EN_RPU = H) or
disconnected when EN_RPU = Low.
12 C8_A INPUT This pin controls the card #A C8 contact. The signal can be either de−multiplexed, at MPU
level, or is multiplexed with C8_B, depending upon the MUX_MODE logic state.
When MUX_MODE = High, this pin provides an access to either card A or B C8 channel
by means of CARD_SEL selection bit.
The associated pull up resistor is either connected to V
CC
(EN_RPU = H) or
disconnected when EN_RPU = Low.
13 CLOCK_IN_A Clock Input,
High Impedance
The signal present on this pin comes from either the MCU master clock, or from any
signal fulfilling the logic level and frequency specifications. This signal is fed to the
internal clock selection circuit prior to be connected to the external smart card #A. Each
of the external card can have different division ratio, depending upon the state of the
CRD_SEL pin and associated programming bits. The built−in circuit can be programmed
to 1/1, 1/2, 1/4 or 1/8 frequency division ratio.
This input is valid and routed to either CRD_CLK_A _DIVIDER or
CRD_CLK_B_DIVIDER regardless of the MUX_MODE state, depending upon the
CLK_D_A/CRD_D_B and CARD_SEL programmed states (Table 1).
Although this input supports the signal coming from a crystal oscillator, care must be
observed to avoid digital levels outside the specified V
IH
/V
IL
range. Similarly, the input
clock signal shall have rise and fall times compatible with the operating frequency.
14 ANLG_GND POWER This pin is the ground reference for both analog and digital signals and must be
connected to the system Ground. Care must be observed to provide a copper PCB layout
designed to avoid small signals and power transients sharing the same track. Good high
frequency techniques are strongly recommended.
15 CLOCK_IN_B Clock Input,
High Impedance
The signal present on this pin comes from either the MCU master clock, or from any
signal fulfilling the logic level and frequency specifications. This signal is fed to the
internal clock selection circuit prior to be connected to the external smart card #B. Each
of the external card can have different division ratio, depending upon the state of the
CRD_SEL pin and associated programming bits. The built−in circuit can be programmed
to 1/1, 1/2, 1/4, or 1/8 frequency division ratio.
This input is valid and routed to either CRD_CLK_B_DIVIDER or CRD_CLK_A_DIVIDER
regardless of the MUX_MODE state, depending upon the CRD_D_B/CRD_D_A and
CARD_SEL programmed states (Table 1).
Although this input supports the signal coming from a crystal oscillator, care must be
observed to avoid digital levels outside the specified V
IH
/V
IL
range. Similarly, the input
clock signal shall have rise and fall times compatible with the operating frequency.
16 C8_B INPUT This pin controls the card #B C8 contact. The signal can be either de −multiplexed, at
MPU level, or is multiplexed with C8_A, depending upon the MUX_MODE logic state.
When MUX_MODE = High, this pin is internally disable, a pull up resistor is connected to
V
CC
(regardless of the logic state of EN_RPU is), and the access to card B takes place
by C8_A associated with CARD_SEL selection bit.
The associated pull up resistor is either connected to V
CC
(EN_RPU = H) or
disconnected when EN_RPU = Low.
17 C4_B INPUT This pin controls the card #B C4 contact. The signal can be either de −multiplexed, at
MPU level, or is multiplexed with C8_A, depending upon the MUX_MODE logic state.
When MUX_MODE = High, this pin is internally disable, a pull up resistor is connected to
V
CC
, (regardless of the logic state of EN_RPU), and the access to card B takes place by
C4_A associated with CARD_SEL selection bit.
The associated pull up resistor is either connected to V
CC
(EN_RPU = H) or
disconnected when EN_RPU = Low.
NCN6004A
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6
PIN DESCRIPTION (continued)
Pin DescriptionTypeSymbol
18 RESET_B INPUT The signal present on this pin is translated to the RST pin of the external smart card #B.
The CS signal must be Low to valid the RESET function, regardless of the selected card.
Assuming the mP provides two independent lines to control the RESET pins, and
MUX_MODE = Low, the NCN6004A can control two cards simultaneously.
When MUX_MODE = High, this pin is internally disable, a pull up resistor is connected to
V
CC
, (regardless of the logic state of EN_RPU), and the access to card B takes place by
RESET_A associated with CARD_SEL selection bit.
The associated pull up resistor is either connected to V
CC
(EN_RPU = H) or
disconnected when EN_RPU = Low.
19 I/O_B INPUT/OUTPUT This pin carries the data transmission between an external microcontroller and the
external smart card #B.
A built−in bi−directional level translator adapts the signal flowing between the card and
the MCU. The level translator is enabled when CS = Low. The signal present on this pin
is latched when CS = High. Since a dedicated line is used to communicate the data
between the mP and the smart card, (assuming MUX_MODE = Low) the user can
activate the two channels simultaneously, assuming the mP provides a pair of I/O lines.
When MUX_MODE = High, this pin is internally disable, the pull up resistor is connected
to V
CC
, (regardless of the logic state of EN_RPU), and the access to card B takes place
by I/O_A associated with CARD_SEL selection bit.
20 CRD_DET_A INPUT This pin senses the signal coming from the external smart card connector to detect the
presence of card #A. The polarity of the signal is programmable as Normally Open or
Normally Close switch. The logic signal will be activated when the level is either Low or
High, with respect to the polarity defined previously. By default, the input is Normally
Open. A built−in circuit prevents uncontrolled short pulses to generate an INT signal.
The digital filter eliminates pulse width below 50ms (see spec).
21 CRD_C8_A OUTPUT This pin controls the card #A C8 contact, according to the ISO7816 specifications. A
built−in level shifter is used to adapt the card and the mC, regardless of the power supply
voltage of each signals.
The signal present at this pin is latched upon either CARD_SEL =L, or CS = H or
PGM = L, and resume to a transparent mode when card #A is selected and operates in
the transfer mode.The pin is hardwired to zero, the bias being provided by the V
CC
supply, when either the V
CC
voltage drops below 2.7 V, or during the CRD_VCC_A
startup time.
22 CRD_C4_A OUTPUT This pin controls the card #A C4 contact, according to the ISO7816 specifications. A
built−in level shifter is used to adapt the card and the MCU, regardless of the power
supply voltage of each signals.
The signal present at this pin is latched upon either CARD_SEL = L, or CS = H, or
PGM = L, and resume to a transparent mode when card #A is selected and operates in
the transfer mode.
The pin is hardwired to zero, the bias being provided by the V
CC
supply, when either the
V
CC
voltage drops below 2.7 V, or during the CRD_VCC_A startup time.
23 CRD_RST_A OUTPUT This pin is connected to the external smart card #A to support the RESET signal. A
built−in level shifter is used to adapt the card and the MCU, regardless of the power
supply voltage of each signals.
The signal present at this pin is latched upon either CARD_SEL = Low, or when CS or
PGM returns to a High, and resume to a transparent mode when card #A is selected. The
pin is hardwired to zero, the bias being provided by the V
CC
supply, when either the V
CC
voltage drops below 2.7 V, or during the CRD_VCC_A startup time.
24 CRD_IO_A INPUT/OUTPUT This pin carries the data serial connection between the external smart card #A and the
microcontroller. A built−in bidirectional level shifter is used to adapt the card and the
MCU, regardless of the power supply voltage of each signals.
This pin is biased by a pull up resistor connected to CRD_VCC_A. When CS = High, the
CRD_IO_A holds the previous I/O logic state and resume to a normal operation when this
pin is reactivated.
The pin is hardwired to zero, the bias being provided by the V
CC
supply, when either the
V
CC
voltage drops below 2.7 V, or during the CRD_VCC_A start−up time.
25 PWR_GND POWER This pin carries the power current flow coming from the built in DC/DC converters. It is
associated with the external card # A. It must be connected to the system Ground and care
must be observed at PCB layout level to avoid the risk of spike voltages on the logic lines.
26 L2_A POWER Connects one side of the external DC/DC converter inductor #A (Note 1).
27 L1_A POWER Connects one side of the external DC/DC converter inductor #A (Note 1).
1. The external inductors shall preferably have the same values. Depending upon the power absorbed by the load, the inductor can range
from 10 mH to 47 mH. To achieve the highest yield, the inductor shall have an ESR < 1.0 W.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P40

NCN6004AFTBR2

Mfr. #:
Buy NCN6004AFTBR2
Manufacturer:
ON Semiconductor
Description:
I/O Controller Interface IC 2.7V POS/ATM Smart
Lifecycle:
New from this manufacturer.
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