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Table 3. Status Pins Data
STATE
(HEX)
PGM A3 A2 A1 A0 CARD_SEL STATUS #A STATUS #B
00 1 X X 0 0 X Vcc_V
bat
_OK Pass = Low
VCC_OK Fail = High
01 1 X X 0 1 1 CRD_VCC_A In Range
Pass = High Fail =Low
02 1 X X 1 0 1 CRD_VCCA Overloaded
Pass = High Fail = Low
03 1 X X 1 1 1 CRD_DET_A
Card Present = High
00 1 X X 0 0 X VCC_OK Pass = Low
VCC_OK Fail = High
01 1 X X 0 1 0 CRD_VCC_B In Range
Pass = High Fail =Low
02 1 X X 1 0 0 CRD_VCC_B Overloaded
Pass = High Fail = Low
03 1 X X 1 1 0 CRD_DET_A
Card Present = High
*The STATUS register is not affected when the NCN6004A operates in any of the programming mode.
Initialized conditions upon start−up are depicted by bold characters in Table 2 and Table 4.
Vbat
2.10 V
2.00 V
2.70 V
3.30 V
Vbat_OK
Vbat STATUS
Max. ANLG_VCC Under Voltage
Min. ANLG_VCC Under Voltage
Typical ANLG_VCC Operating Voltage
The input power supply voltage monitoring applies to the card selected.
Figure 5. Reading ANLG_VCC Status (monitoring ANLG_VCC input voltage)
SYSTEM STATES UPON UPON START−UP
Table 4. Operating Conditions Upon Start−up
CRD_VCC_A 3.0 V
CRD_VCC_B 3.0 V
CRD_CLK_A 1/1 Ratio
CRD_CLK_B 1/1 Ratio
CRD_CLK_A START (clock is valid)
CRD_CLK_B START (clock is valid)
CRD_CLK_A Low Speed Slope
CRD_CLK_B Low Speed Slope
CLOCK Route Direct (CLK_A A, CLK_B B)
Depending upon the logic state at turn on present on
pin 44, the system will run into a parallel mode
(MUX_MODE = L) or a multiplexed mode
(MUX_MODE = H). It is not possible to change the logic
state once the system is running.
Similarly, depending upon the logic state present pin 45,
the internal pull up resistors (I/O_A and I/O_B line) will be
either connected to ANLG_VCC voltage (EN_RPU = H) or
disconnected (EN_RPU = L). It is not possible to change this
operating condition once the system is running.
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PARALLEL/MULITPLEXED OPERATION MODES
The logic input MUX_MODE, pin 44, provides a way to
select the operation mode of the NCN6004A. Depending
upon the logic level, the device operates either in a parallel
mode (all the card pins, on the mP side, are fully independent)
or in multiplexed mode (all the logic card pins, on the mP
side, share a common bus). Figure 6 shows a simplified
schematic of the multiplex circuit built in the NCN6004A
chip.
Figure 6. Simplified MUX_MODE Logic and Multiplex Circuit
13
10
11
12
9
19
18
17
16
15
RESET_A
C4_A
C8_A
CLK_IN_A
I/O_A
I/O_B
C8_B
C4_B
REST_B
CLK_IN_B
15
15
MUX_MODE
CARD_SEL
CARD_A
GATING
BUFFERS
BUFFERS
BUFFER
BUFFER
BUFFER
CARD_B
GATING
I/O_A
BUFFER
I/O_B
CARD_B
CARD_A
CLK_A
Q1
Q2
CLK_B
Q3
A
A
A
B
B
B
CLOCK DIVIDERS
23
22
21
24
37
38
39
40
30
31
Q4
MULTIPLEXER
& MULTIPLEXER
In both case, the device is programmed by means of the
common logic controls pins (A0, A1, A2, A3, PGM,
PWR_ON, CARD_SEL and CS). On the other hand, the
logic status returned by the interface (STATUS pin 46) is
shared by the two channels and can be read independently
by setting CARD_SEL accordingly.
The card related signals connected on the mC side are
multiplexed or independent, depending upon the
MUX_MODE state as described here below.
MUX_MODE = Low PARALLEL MODE
When pin 44 is low, the device operates in the parallel
mode. The transfer gate Q4 and the multiplexer circuit are
disconnected and all the data will be carried out through their
respective paths. The switches Q1, Q2 and Q3 are flipped to
the B position, thus providing a direct connection from port
B control signals to CARD_B
All the CARD_A and CARD_B signals are independent
and both cards can operate simultaneously, the data
transaction can take place at the same time and processed
independently. Of course, the microcontroller must have the
right data bus available to handle this process.
However, it is not possible to change the operating mode
once the system has been started. If such a function is
needed, one must pull down the related NCN6004A power
supply, change the MUX_MODE logic level, and re−start
the interface.
MUX_MODE = High MULTIPLEXED MODE
When pin 44 is High, the device operates in a multiplexed
mode and all the card signals are shared between CARD_A
and CARD_B, except the input clocks which are
independent at any time. The RST_B, C4_B and C8_B pins
are preferably left open at PCB level. The I/O_B pin must be
left open and cannot be connected to any external signal or
bias voltages.
The transfer gate Q4 is switched ON and, depending upon
the CARD_SEL logic level, the I/O data will be transferred
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to either CARD_A or CARD_B. It is neither possible to
connect directly I/O_A to I/O_B nor to connect the I/O_B
pin to ground or voltage supply.
The multiplexer is activated and the CARD_SEL signal is
used to select the card in use for a given transaction. The
switches Q1, Q2 and Q3 and swapped to the A position, thus
providing a path for the control signals applied to the
CARD_A side.
When the CARD_SEL signal flips from one card to the
other, the previous logic states of the on going card are
latched in the chip and the related output card pin are
maintained at the appropriate levels. When the system
resumes to the previous card, the latches return to the
transparent operation and the signals presented by the mP
take priority over the previously latched states.
On the other hand, the input clocks (CLK_IN_A and
CLK_IN_B) are maintained independent and can be routed
to either CARD_A or CARD_B according to the
programming functions given in Table 2.
CARD POWER SUPPLY TIMING
When the PWR_ON signal is high, the associated
CRD_VCC_A or CRD_VCC_B power supply rise time
depends upon the current capability of the DC/DC converter
together with the external inductors L1/L2 and the reservoir
capacitor connected across each card power supply pin and
GROUND.
On the other hand, at turn off, the CRD_VCC_A and
CRD_VCC_B fall times depend upon the external reservoir
capacitor and the peak current absorbed by the internal
NMOS device built across each CRD_VCC_A/
CRD_VCC_B and GROUND. These behaviors are depicted
by Figure 7, assuming a 10 mF output capacitor.
Since none of these parameters can have infinite values,
the designer must take care of these limits if the t
ON
or the
t
OFF
provided by the data sheets does not meet his
requirement.
t
V
CRD_VCC = 5 V
CRD_VCC = 4.75 V
CRD_VCC = 0.40 V
Turn ON Shut OFF
500 ms Max
250 ms Max
Figure 7. Card Power Supply Turn ON and Shut
OFF Typical Timings
POWER DOWN OPERATION
The power down mode can be initiated by either the
external MPU or by the internal error condition. The
communication session is terminated immediately,
according to the ISO7816−3 sequence. On the other hand,
the MPU can run the Stand By mode by forcing CS = H,
leaving the chip in the previous operating mode.
When the card is extracted, the interface will detect the
operation and will automatically run the Power Down
Sequence of the related card as described by the ISO/CEI
7816−3 sequence depicted in Figure 8 and illustrated by the
oscillogram in Figure 9.
CRD_VCC
CRD_RST
CRD_CLK
CRD_IO
CARD EXTRACTION DETECTED
T
CRD_C4
CRD_C8
CRD_DET
Internal Delay
400 ns typ.
Figure 8. Card Power Down Sequence
Force RST to Low
Force CLK to Low, unless it is already in this state
Force C4 and C8 to Low
Force CRD_IO to Low
Shut Off the CRD_VCC Supply

NCN6004AFTBR2

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
I/O Controller Interface IC 2.7V POS/ATM Smart
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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