NCN6004A
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30
The input clock A and B can be re routed to either
CRD_CLK_A or CRD_CLK_B output pins by using the
programming function as defined in Table 2 and Table 7. The
clock signals can have any frequency value necessary to
handle a given type of card (asynchronous or synchronous).
These clock signals can be multiplexed at any time, but the
system must be locked in a safe state prior to make such a
change. In particular, the designer must make sure that A and
B cards can support such a hot change prior to change the
related clocks.
Table 7. Programming Clock Routing
STATE CS PGM A3 A2 A1 A0 CARD_SEL CRD_CLK_A CRD_CLK_B
0E 0 0 1 1 1 0 1 CLK_D_A − Default
0F 0 0 1 1 1 1 1 CLK_D_B − −
0E 0 0 1 1 1 0 0 − CLK_D_B Default
0F 0 0 1 1 1 1 0 − CLK_D_A −
On the other hand, the slope of the CRD_CLK_x signal
can be set to either FAST or SLOW, depending upon the
frequency of the output clock. This selection is achieved by
programming the chip according to Table 8.
Table 8. Output Clock Slope Selection
STATE CS PGM A3 A2 A1 A0 CARD_SEL CLOCK SLOPE
$03 0 0 0 0 1 1 1 SLOW Default
$0B 0 0 1 0 1 1 1 FAST −
$03 0 0 0 0 1 1 0 SLOW Default
$0B 0 0 1 0 1 1 0 FAST −
Figure 30. Typical Rise and Fall Time in Fast and
Slow Operating Mode
PARALLEL OPERATION
When two or more NCN6004A parts operate in parallel on
a common digital bus, the Chip Select pin allows the
selection of one chip from the bank of the paralleled devices.
Of course, the external MPU shall provide one unique CS
line for each of the NCN6004A considered interface. When
a given interface is selected by CS = L, all the logic inputs
becomes active, the chip can be programmed or/and the
external card can be accessed. When CS = H, all the input
logic pins are in the high impedance state, thus leaving the
bus available for other purpose.
The pull up resistors connected on each logic input lines on
the MPU side (see block diagram in Figure 30), can be either
activated (connected to V
CC
) or disconnected, depending
upon the logic state present at EN_RPU, pin 45. When these
resistors are disconnected, it is the system responsibility to
set up the external pull up resistors according to the
application’s requirements.
When the device operates in the multiplexed mode
(MUX_MODE = High), the internal card #B pull up
resistors are connected to V
CC
, regardless of the EN_RPU
logic state.
On the other hand, when CS = H, the CRD_IO and
CRD_RST hold the previous I/O and RESET logic state, the
CRD_CLK being either active or stopped and the
CRD_VCC output voltage will maintain is previous value,
according to the programmed state forced by the MPU.
