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On the other hand, the Power Down sequence is
automatically activated when the V
bat
voltage drops below
the VCC_OK level, regardless of the logic conditions
present on the control pins, or when the related
CRD_VCC_x output voltage reaches the overload
condition.
Figure 9. Power Down Sequence
Figure 10. Power Down Sequence: Timing Details
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CARD DETECTION
The card detector circuit provides a constant low current to
bias the CRD_DET_A and CRD_DET_B pins, yielding a
logic High when no card is present and the external switch is
Normally Open type. The internal logic associated with pins
20 and 41 provides a programmable selection of the slope
card detection. The transition is filtered out by the internal
digital filter circuit, avoiding false interrupt. In addition to
the typical 50 ms delay, the MPU shall provide an additional
delay to cope with the mechanical stabilization of the card
interface (typically 1 ms), prior to valid the CRD_VCC_A or
CRD_VCC_B supply.
When a card is inserted, the detector circuit asserts
INT = Low as depicted before, the external mP being
responsible to clear the interrupt signal, taking the
necessaries actions. When the NCN6004A detects a card
extraction, the power down sequence is automatically
activated for the related interface section, regardless of the
PWR_ON state, and the INT pin is asserted Low. It is up to
the external MPU to clear this interrupt by pulsing the CS
pin.
CRD_DET_A
STATUS
A0
A1
INTERRUPT CARD IDENTIFICATION
CLEAR INTERRUPT
CARD PRESENT: STATUS = 1
CARD NOT PRESENT: STATUS = 0
CARD EXTRACTED
50 ms < T < 150 ms
High
High
High
50 ms < T < 150 ms
CLEAR INTERRUPT
A2
A3
CARD_SEL
High = Card A
IRRELEVANT
IRRELEVANT
Figure 11. Typical Interrupt Sequence
PGM
INT
CS
ACKNOWLEDGE & PROCESSING
The interrupt signal can be cleared either by a positive
going slope on the Chip Select pin as depicted in Figure 11,
or by forcing the PWR_ON signal High (keeping CS = Low)
for the related card.
The polarity of the card detection switch can be either
Normally Open or Normally Close and is software
controlled as defined here below and in Table 2.
Table 5. Card Detection Polarity
CS PGM A3 A2 A1 A0 CARD_SEL CRD_DET_A CRD_DET_B
1 X X X X X X Qn −1 Qn −1
0 1 X X X X X Qn −1 Qn −1
0 0 1 1 0 0 1 Normally Open Qn −1
0 0 1 1 0 1 1 Normally Close Qn −1
0 0 1 1 0 0 0 Qn −1 Normally Open
0 0 1 1 0 1 0 Bn −1 Normally Close
*The polarity change is validated upon the next positive PGM transient.
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POWER MANAGEMENT
The main purpose of the power management is to provides
the necessary output voltages to drive the 1.80 V, 3.0 V or
5.0 V smart card types. On top of that, the DC/DC converter
efficiency must absorb a minimum current on the V
bat
supply.
Beside the power conversion, in the Stand by mode
(PWR_ON = L), the power management provides energy to
the card detection circuit only. All the card interface pins are
forced to ground potential, saving as much current as
possible out of the battery supply.
In the event of a power up request coming from the
external MPU (CARD_SEL =H/L, PWR_ON = H, CS = L),
the power manager starts the DC/DC converter related to the
selected interface section.
When the selected section (either CRD_VCC_A or
CRD_VCC_B) voltage reaches the programmed value
(1.8 V, 3.0 V or 5.0 V), the circuit activates the card signals
according to the following sequence:
CRD_VCC_x CRD_IO_x CRD_C4_x CRD_C8_x
CRD_CLK_x CRD_RST_x
The logic level of the data lines are asserted High or Low,
depending upon the state forced by the external MPU, when
the start−up sequence is completed. Under no situation the
NCN6004A shall automatically launch a smart card ATR
sequence.
At the end of the transaction, asserted by the MPU
(CARD_SEL = H/L, PWR_ON = L, CS = L), or under a card
extraction, the ISO7816−3 power down sequence takes
place:
CRD_RST_x CRD_CLK_x CRD_C4_x
CRD_C8_x CRD_IO_x CRD_VCC_x
When CS = H, the bi−directional I/O lines (pins 9 and 19)
are forced into the High impedance mode to avoid signal
collision with any data coming from the external MPU.
OUTPUT VOLTAGE PROGRAMMING
The internal logic provides a reliable circuit to activate
any of the DC/DC converters safely. In particular, the Turn
On/Turn Off of these converters is edge sensitive and
controlled by the rising/falling edges of the PWR_ON signal
applied with Chip Select pin Low. The CARD_SEL signal
is used to select either CRD_VCC_A or CRD_VCC_B as
defined by the functions programming in Table 2.
PWR_ON
CRD_VCC Rise Time
CRD_VCC No Change
CRD_VCC_A PWR DOWN
VCCtoff
CARD_SEL
CRD_VCC_A
CRD_VCC_B
SET
RESET
VCCton
VCCton
see note
Note : minimum 1 ms delay before to send a power Off command to the same
selected output is recommended.
Figure 12. Card Power Supply Controls
CS
Although it is possible to change the output voltage
straightly from 5.0 V to 1.80 V, care must be observed as the
stabilization time will be relatively long if no current is
absorbed from the related output pin.
According to the typical sequence depicted, it is not
possible to program simultaneously the two DC/DC
converters, but two separate sequences must take place. On
top of that, since the circuit is edge sensitive, the PWR_ON
signal must present such a transient when a given state is
expected for the converter. The PWR_ON and CS timings
definitions are given in Figure 13.

NCN6004AFTBR2

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
I/O Controller Interface IC 2.7V POS/ATM Smart
Lifecycle:
New from this manufacturer.
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