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AD9822JRSZ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20
Complete 14-Bit
CCD/CIS Signal Processor
AD9822
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703
© 2005 Analog Devices, Inc. All rights reserved.
FEATURES
14-bit 15 MSPS ADC
No missing codes guaranteed
3-channel operation up to 15 MSPS
1-channel operation up to 12.5 MSPS
Correlated double sampling
1–6× programmable gain
±350 mV programmable offset
Input clamp circuitry
Internal voltage reference
Multiplexed byte-wide output (8 + 6 format)
3-wire serial digital interface
3 V/5 V digital I/O compatibility
28-Lead SOIC or SSOP
Low power CMOS: 385 mW (typ)
Power-down mode: <1 mW
APPLICATIONS
Flatbed document scanners
Film scanners
Digital color copiers
Multifunction peripherals
GENERAL DESCRIPTION
The AD9822 is a complete analog signal processor for CCD
imaging applications. It features a 3-channel architecture designed
to sample and condition the outputs of trilinear color CCD
arrays. Each channel consists of an input clamp, correlated double
sampler (CDS), offset DAC, and programmable gain amplifier
(PGA) multiplexed to a high performance 14-bit ADC.
The CDS amplifiers may be disabled for use with sensors such
as contact image sensors (CIS) and CMOS active pixel sensors,
which do not require CDS.
The 14-bit digital output is multiplexed into an 8-bit output
word that is accessed using two read cycles. The internal
registers are programmed through a 3-wire serial interface and
provide adjustment of the gain, offset, and operating mode.
The AD9822 operates from a single 5 V power supply,
consumes 385 mW of power typically, and is packaged in a
28-lead SOIC or SSOP.
FUNCTIONAL BLOCK DIAGRAM
14 8
BAND GAP
REFERENCE
CONFIGURATION
REGISTER
MUX
REGISTER
66
99
GAIN
REGISTERS
OFFSET
REGISTERS
DIGITAL
CONTROL
INTERFACE
INPUT
CLAMP
BIAS
AD9822
DRVDD DRVSSAVDD AVSSCAPT CAPBAVDD AVSS CML
OEB
DOUT
ADCCLKCDSCLK2CDSCLK1
OFFSET
VINB
VING
VINR
9-BIT
DAC
00623-001
SCLK
SLOAD
SDATA
9-BIT
DAC
9-BIT
DAC
CDS PGA
PGA
PGA
CDS
CDS
3:1
MUX
14-BIT
ADC
14:8
MUX
BLUE
GREEN
RED
BLUE
GREEN
RED
Figure 1.
AD9822
Rev. B | Page 2 of 20
TABLE OF CONTENTS
Specifications..................................................................................... 3
Analog Specifications................................................................... 3
Digital Specifications ................................................................... 4
Timing Specifications .................................................................. 5
Absolute Maximum Ratings............................................................ 6
Thermal Characteristics .............................................................. 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Te rm ino lo g y ...................................................................................... 8
Functional Description .................................................................. 12
3-Channel CDS Mode................................................................ 12
3-Channel SHA Mode................................................................ 12
1-Channel CDS Mode ............................................................... 12
1-Channel SHA Mode ............................................................... 12
Internal Register Descriptions.................................................. 13
Circuit Operation ........................................................................... 15
Analog Inputs—CDS Mode...................................................... 15
External Input Coupling Capacitors........................................ 15
Analog Inputs—SHA Mode...................................................... 16
Programmable Gain AmplifierS (PGA).................................. 16
Applications..................................................................................... 17
Circuit and Layout Recommendations ................................... 17
Outline Dimensions....................................................................... 18
Ordering Guide .......................................................................... 18
REVISION HISTORY
2/05—Rev. A to Rev. B
Changes to Format .............................................................Universal
Changes to Ordering Guide .......................................................... 18
Updated Outline Dimensions....................................................... 18
12/99—Rev. 0 to Rev. A
AD9822
Rev. B | Page 3 of 20
SPECIFICATIONS
ANALOG SPECIFICATIONS
T
MIN
to T
MAX
, AVDD = 5 V, DRVDD = 5 V, CDS mode, f
ADCCLK
= 15 MHz, f
CDSCLK1
= f
CDSCLK2
= 5 MHz, PGA gain = 1, unless otherwise noted.
Table 1.
Parameter Min Typ Max Unit
MAXIMUM CONVERSION RATE
3-Channel Mode with CDS 15 MSPS
1-Channel Mode with CDS 12.5 MSPS
ACCURACY (ENTIRE SIGNAL PATH)
ADC Resolution 14 Bits
Integral Nonlinearity (INL) −17.0/+3.5 LSB
INL @ 6 MHz −10.5/+1.5 LSB
Differential Nonlinearity (DNL) −0.65/+0.75 LSB
DNL @ 6 MHz −1.0 −0.6/+0.65 +1.1 LSB
No Missing Codes 14 Bits
No Missing Codes @ 6 MHz 14 Bits
Offset Error −240 −19 +200 mV
Gain Error −1.4 +3.5 +6.9 % FSR
ANALOG INPUTS
Input Signal Range
1
2.0 V p-p
Allowable Reset Transient
1
1.0 V
Input Limits
2
AVSS − 0.3 AVDD + 0.3 V
Input Capacitance 10 pF
Input Bias Current 10 nA
AMPLIFIERS
PGA Gain at Minimum 1 V/V
PGA Gain at Maximum 5.7 V/V
PGA Gain Resolution
2
64 Steps
PGA Gain Monotonicity Guaranteed
Programmable Offset at Minimum −350 mV
Programmable Offset at Maximum +350 mV
Programmable Offset Resolution 512 Steps
Programmable Offset Monotonicity Guaranteed
NOISE AND CROSSTALK
Total Output Noise @ PGA Minimum 1.5 LSB rms
Total Output Noise @ PGA Maximum 6.0 LSB rms
Channel-to-Channel Crosstalk @ 6 MHz <1 LSB
POWER SUPPLY REJECTION
AVDD = 5 V ± 0.25 V 0.063 0.9 % FSR
DIFFERENTIAL VREF (@ 25°C)
CAPT to CAPB (2 V ADC Full-Scale Range) 0.94 1.0 1.06 V
TEMPERATURE RANGE
Operating 0 +70 °C
Storage −65 +150 °C
POWER SUPPLIES
AVDD 4.75 5.0 5.25 V
DRVDD 3.0 5.0 5.25 V
OPERATING CURRENT
AVDD 73 mA
DRVDD 4 mA
Power-Down Mode Current 150 µA
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20

AD9822JRSZ

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Description:
Analog Front End - AFE 14-Bit CCD/CIS Signal Processor
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