AD9822JRSZ Datasheet AD9822JRSZRL, AD9822JRSZ | P13-P15

AD9822

Rev. B | Page 13 of 20

INTERNAL REGISTER DESCRIPTIONS

Table 6. Internal Register Map

A2 A1 A0 D8 D7 D6 D D4 D3 D2 D1 D0

Configuration 0 0 0 0 0 VREF 3Ch/1Ch CDS On Clamp Pwr Dn 0 0

MUX 0 0 1 0 RGB/BGR Red Green Blue 0 0 0 0

Red PGA 0 1 0 0 0 0 MSB LSB

Green PGA 0 1 1 0 0 0 MSB LSB

Blue PGA 1 0 0 0 0 0 MSB LSB

Red Offset 1 0 1 MSB LSB

Green Offset 1 1 0 MSB LSB

Blue Offset 1 1 1 MSB LSB

Configuration Register

The Configuration Register controls the AD9822’s operating mode and bias levels. Bits D8, D1, and D0 should always be set low. Bit D7

sets the full-scale voltage range of the AD9822’s ADC to either 4 V (high) or 2 V (low). Bit D6 controls the internal voltage reference. If the

AD9822’s internal voltage reference is used, this bit is set high. Setting Bit D6 low disables the internal voltage reference, allowing an

external voltage reference to be used. Bit D5 configures the AD9822 for either the 3-channel (high) or 1-channel (low) mode of operation.

Setting Bit D4 high enables the CDS mode of operation and setting this bit low enables the SHA mode of operation. Bit D3 sets the dc bias

level of the AD9822’s input clamp. This bit should always be set high for the 4 V clamp bias, unless a CCD with a reset feedthrough

transient exceeding 2 V is used. If the 3 V clamp bias level is used, the peak-to-peak input signal range to the AD9822 is reduced to 3 V

maximum. Bit D2 controls the power-down mode. Setting Bit D2 high places the AD9822 into a very low power “sleep” mode. All register

contents are retained while the AD9822 is in the power-down state.

Table 7. Configuration Register Settings

D8 D7 D6 D5 D4 D3 D2 D1 D0

Set to 0 Set to 0 Internal VREF No. of Channels CDS Operation Input Clamp Bias Power-Down Set to 0 Set to 0

1 = Enabled

1 = 3-Ch Mode

1 = CDS Mode

1 = 4 V

1 = On

0 = Disabled 0 = 1-Ch Mode 0 = SHA Mode 0 = 3 V 0 = Off (Normal)

Power-on default value.

MUX Register

The MUX register controls the sampling channel order in the AD9822. Bits D8, D3, D2, D1, and D0 should always be set low. Bit D7 is

used when operating in 3-channel mode. Setting Bit D7 high sequences the MUX to sample the red channel first, then the green channel,

and then the blue channel. When in this mode, the CDSCLK2 pulse always resets the MUX to sample the red channel first (see Figure 3).

When Bit D7 is set low, the channel order is reversed to blue first, green second, and red third. The CDSCLK2 pulse always resets the

MUX to sample the blue channel first. Bits D6, D5, and D4 are used when operating in 1-channel mode. Bit D6 is set high to sample the

red channel. Bit D5 is set high to sample the green channel. Bit D4 is set high to sample the blue channel. The MUX remains stationary

during 1-channel mode.

Table 8. MUX Register Settings

D8 D7 D6 D5 D4 D3 D2 D1 D0

Set to 0 3-Channel Select 1-Channel Select 1-Channel Select 1-Channel Select Set to 0 Set to 0 Set to 0 Set to 0

1 = R-G-B

1 = RED

1 = GREEN 1 = BLUE

0 = B-G-R 0 = Off 0 = Off

0 = Off

Power-on default value.

AD9822

Rev. B | Page 14 of 20

PGA Gain Registers

There are three PGA registers for individually programming the gain in the red, green, and blue channels. Bits D8, D7, and D6 in each

register must be set low, and Bits D5 through D0 control the gain range in 64 increments. See Figure 15 for the PGA gain vs. the PGA

register code. The coding for the PGA registers is straight binary, with an all 0s word corresponding to the minimum gain setting (1×)

and an all 1s word corresponding to the maximum gain setting (5.7×).

Table 9. PGA Gain Register Settings

D8 D7 D6 D5 D4 D3 D2 D1 D0

Set to 0 Set to 0 Set to 0 MSB LSB Gain (V/V) Gain (dB)

0 0 0 0 0 0 0 0 0

1.0 0.0

0 0 0 0 0 0 0 0 1 1.013 0.12

• • •

0 0 0 1 1 1 1 1 0 5.4 14.6

0 0 0 1 1 1 1 1 1 5.7 15.1

Power-on default value.

Offset Registers

There are three PGA registers for individually programming the offset in the red, green, and blue channels. Bits D8 through D0 control

the offset range from −350 mV to +350 mV in 512 increments. The coding for the offset registers is sign magnitude, with D8 as the sign

bit. Table 10 shows the offset range as a function of the Bits D8 through D0.

Table 10. Offset Register Settings

D8 (MSB) D7 D6 D5 D4 D3 D2 D1 D0 (LSB) Offset (mV)

0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 1 +1.2

• •

0 1 1 1 1 1 1 1 1 +350

1 0 0 0 0 0 0 0 0 0

1 0 0 0 0 0 0 0 1 −1.2

• •

1 1 1 1 1 1 1 1 1 −350

Power-on default value.

AD9822

Rev. B | Page 15 of 20

CIRCUIT OPERATION

ANALOG INPUTS—CDS MODE

Figure 10 shows the analog input configuration for the CDS

mode of operation. Figure 11 shows the internal timing for the

sampling switches. The CCD reference level is sampled when

CDSCLK1 transitions from high to low, opening S1. The CCD

data level is sampled when CDSCLK2 transitions from high to

low, opening S2. S3 is then closed, generating a differential

output voltage representing the difference between the two

sampled levels.

The input clamp is controlled by CDSCLK1. When CDSCLK1 is

high, S4 closes and the internal bias voltage is connected to the

analog input. The bias voltage charges the external 0.1 µF input

capacitor, level-shifting the CCD signal into the AD9822’s input

common-mode range. The time constant of the input clamp is

determined by the internal 5 kΩ resistance and the external

0.1 µF input capacitance.

AD9822

2pF

CML

AVDD

5kΩ

1.7kΩ

VINR

OFFSET

0.1µF

CCD SIGNA

0.1µF1µF

2.2kΩ

6.9kΩ

INPUT CLAMP LEVEL

IS SELECTED IN THE

CONFIGURATION

00362-011

Figure 10. CDS Mode Input Configuration (All Three Channels are Identical)

CDSCLK1

CDSCLK2

(INTERNAL)

S1, S4 CLOSED S1, S4 CLOSED

S2 CLOSED S2 CLOSED

S3 CLOSED S3 CLOSED

S3 OPEN

S2 OPEN

S1, S4 OPEN

00623-012

Figure 11. CDS Mode Internal Switch Timing

EXTERNAL INPUT COUPLING CAPACITORS

The recommended value for the input coupling capacitors is

0.1 µF. While it is possible to use a smaller capacitor, this larger

value is chosen for several reasons:

• Signal Attenuation: The input coupling capacitor creates a

capacitive divider with a CMOS integrated circuit’s input

capacitance, attenuating the CCD signal level. CIN should be

large relative to the IC’s 10 pF input capacitance in order to

minimize this effect.

• Linearity: Some of the input capacitance of a CMOS IC is

junction capacitance, which varies nonlinearly with applied

voltage. If the input coupling capacitor is too small, the

attenuation of the CCD signal varies nonlinearly with signal

level. This degrades the system linearity performance.

• Sampling Errors: The internal 2 pF sample capacitors have a

“memory” of the previously sampled pixel. There is a charge

redistribution error between CIN and the internal sample

capacitors for larger pixel-to-pixel voltage swings. As the

value of CIN is reduced, the resulting error in the sampled

voltage increases. With a CIN value of 0.1 µF, the charge

redistribution error is less than 1 LSB for a full-scale, pixel-to-

pixel voltage swing.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P20

AD9822JRSZ

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Analog Front End - AFE 14-Bit CCD/CIS Signal Processor

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AD9822JRSZ

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