AD9822
Rev. B | Page 4 of 20
Parameter Min Typ Max Unit
POWER DISSIPATION
3-Channel Mode 385 450 mW
3-Channel Mode @ 6 MHz 335 410 mW
1-Channel Mode 300 mW
1-Channel Mode @ 6 MHz 250 mW
1
Linear input signal range is from 2 V to 4 V when the CCD’s reference level is clamped to 4 V by the AD9822’s input clamp.
1V TYP
RESET TRANSIENT
4V SET BY INPUT CLAMP (3V OPTION ALSO AVAILABLE)
2V p-p MAX INPUT SIGNAL RANGE
00623-002
2
The PGA gain is approximately linear-in-dB and follows the equation:
[
]
+
=
63
63
7.41
7.5
G
Gain
where G is the register value. See Figure . 15
DIGITAL SPECIFICATIONS
T
MIN
to T
MAX
, AVDD = 5 V, DRVDD = 5 V, CDS mode, f
ADCCLK
= 15 MHz, f
CDSCLK1
= f
CDSCLK2
= 5 MHz, C
L
= 10 pF, unless otherwise noted.
Table 2.
Parameter Symbol Min Typ Max Unit
LOGIC INPUTS
High Level Input Voltage V
IH
2.0 V
Low Level Input Voltage V
IL
0.8 V
High Level Input Current I
IH
10 µA
Low Level Input Current I
IL
10 µA
Input Capacitance C
IN
10 pF
LOGIC OUTPUTS
High Level Output Voltage V
OH
4.5 V
Low Level Output Voltage V
OL
0.1 V
High Level Output Current I
OH
50 µA
Low Level Output Current I
OL
50 µA
AD9822
Rev. B | Page 5 of 20
TIMING SPECIFICATIONS
T
MIN
to T
MAX
, AVDD = 5 V, DRVDD = 5 V.
Table 3.
Parameter Symbol Min Typ Max Unit
CLOCK PARAMETERS
3-Channel Pixel Rate t
PRA
67 ns
1-Channel Pixel Rate t
PRB
80 ns
ADCCLK Pulse Width t
ADCLK
30 ns
CDSCLK1 Pulse Width t
C1
10 ns
CDSCLK2 Pulse Width t
C2
10 ns
CDSCLK1 Falling to CDSCLK2 Rising t
C1C2
0 ns
ADCCLK Falling to CDSCLK2 Rising t
ADC2
0 ns
CDSCLK2 Rising to ADCCLK Rising t
C2ADR
0 ns
CDSCLK2 Falling to ADCCLK Falling t
C2ADF
30 40 ns
CDSCLK2 Falling to CDSCLK1 Rising t
C2C1
30 40 ns
ADCCLK Falling to CDSCLK1 Rising t
ADC1
0 ns
Aperture Delay for CDS Clocks t
AD
2 ns
SERIAL INTERFACE
Maximum SCLK Frequency f
SCLK
10 MHz
SLOAD to SCLK Setup Time t
LS
10 ns
SCLK to SLOAD Hold Time t
LH
10 ns
SDATA to SCLK Rising Setup Time t
DS
10 ns
SCLK Rising to SDATA Hold Time t
DH
10 ns
SCLK Falling to SDATA Valid t
RDV
10 ns
DATA OUTPUT
Output Delay t
OD
8 ns
Three-State to Data Valid t
DV
10 ns
Output Enable High to Three-State t
HZ
10 ns
Latency (Pipeline Delay) 3 (Fixed) Cycles
AD9822
Rev. B | Page 6 of 20
ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter
With
Respect
To Min Max Unit
VIN, CAPT, CAPB AVSS −0.3 AVDD + 0.3 V
Digital Inputs AVSS −0.3 AVDD + 0.3 V
AVDD AVSS −0.5 +6.5 V
DRVDD DRVSS −0.5 +6.5 V
AVSS DRVSS −0.3 +0.3 V
Digital Outputs DRVSS −0.3 DRVDD + 0.3 V
Junction Temperature 150 °C
Storage Temperature −65 +150 °C
Lead Temperature
(10 sec)
300 °C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or other
conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum
ratings for extended periods may affect device reliability.
THERMAL CHARACTERISTICS
28-Lead 300 Mil SOIC
θ
JA
= 71.4°C/W
θ
JC
= 23°C/W
28-Lead 5.3 mm SSOP
θ
JA
= 109°C/W
θ
JC
= 39°C/W
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

AD9822JRSZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog Front End - AFE 14-Bit CCD/CIS Signal Processor
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet