AD9822
Rev. B | Page 7 of 20
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
00623-003
CDSCLK1
CDSCLK2
ADCCLK
OEB
AVDD
28
AVSS
27
VINR
26
OFFSET
25
DRVDD
DRVSS
(MSB) D7
VING
24
CML
23
VINB
22
D6
CAPT
21
D5
CAPB
20
D4
10
AVSS
19
D3
11
AVDD
18
D2
12
SLOAD
17
D1
13
SCLK
16
(LSB) D0
14
SDATA
15
1
2
3
4
5
6
7
8
9
AD9822
TOP VIEW
(Not to Scale)
Figure 2. Pin Configuration
Table 5. Pin Function Descriptions
Pin No. Mnemonic Type
1
Description
1 CDSCLK1 DI CDS Reference Level Sampling Clock.
2 CDSCLK2 DI CDS Data Level Sampling Clock.
3 ADCCLK DI ADC Sampling Clock.
4 OEB DI Output Enable, Active Low.
5 DRVDD P Digital Output Driver Supply.
6 DRVSS P Digital Output Driver Ground.
7 D7 (MSB) DO Data Output MSB. ADC DB13 High Byte, ADC DB5 Low Byte.
8 D6 DO Data Output. ADC DB12 High Byte, ADC DB4 Low Byte.
9 D5 DO Data Output. ADC DB11 High Byte, ADC DB3 Low Byte.
10 D4 DO Data Output. ADC DB10 High Byte, ADC DB2 Low Byte.
11 D3 DO Data Output. ADC DB9 High Byte, ADC DB1 Low Byte.
12 D2 DO Data Output. ADC DB8 High Byte, ADC DB0 Low Byte.
13 D1 DO Data Output. ADC DB7 High Byte, Don’t Care Low Byte.
14 D0 (LSB) DO Data Output LSB. ADC DB6 High Byte, Don’t Care Low Byte.
15 SDATA DI/DO Serial Interface Data Input/Output.
16 SCLK DI Serial Interface Clock Input.
17 SLOAD DI Serial Interface Load Pulse.
18 AVDD P 5 V Analog Supply.
19 AVSS P Analog Ground.
20 CAPB AO ADC Bottom Reference Voltage Decoupling.
21 CAPT AO ADC Top Reference Voltage Decoupling.
22 VINB AI Analog Input, Blue Channel.
23 CML AO Internal Bias Level Decoupling.
24 VING AI Analog Input, Green Channel.
25 OFFSET AO Clamp Bias Level Decoupling.
26 VINR AI Analog Input, Red Channel.
27 AVSS P Analog Ground.
28 AVDD P 5 V Analog Supply.
1
Type: AI = Analog Input, AO = Analog Output, DI = Digital Input, DO = Digital Output, P = Power.
AD9822
Rev. B | Page 8 of 20
TERMINOLOGY
Integral Nonlinearity (INL)
Integral nonlinearity error refers to the deviation of each
individual code from a line drawn from zero scale through
positive full scale. The point used as zero scale occurs ½ LSB
before the first code transition. Positive full scale is defined as a
level 1 ½ LSB beyond the last code transition. The deviation is
measured from the middle of each particular code to the true
straight line.
Differential Nonlinearity (DNL)
An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value; therefore,
every code must have a finite width. No missing codes
guaranteed to 14-bit resolution indicates that all 16384 codes,
respectively, must be present over all operating ranges.
Offset Error
The first ADC code transition should occur at a level ½ LSB
above the nominal zero-scale voltage. The offset error is the
deviation of the actual first code transition level from the ideal
level.
Gain Error
The last code transition should occur for an analog value
1 ½ LSB below the nominal full-scale voltage. Gain error is the
deviation of the actual difference between the first and last code
transitions and the ideal difference between the first and last
code transitions.
Input Referred Noise
The rms output noise is measured using histogram techniques.
The ADC output codes standard deviation is calculated in LSB
and converted to an equivalent voltage, using the relationship
1 LSB = 4 V/16384 = 244 mV. The noise is then referred to the
input of the AD9822 by dividing by the PGA gain.
Channel-to-Channel Crosstalk
In an ideal 3-channel system, the signal in one channel will not
influence the signal level of another channel. The channel-to-
channel crosstalk specification is a measure of the change that
occurs in one channel as the other two channels are varied. In
the AD9822, one channel is grounded and the other two
channels are exercised with full-scale input signals. The
change in the output codes from the first channel is measured
and compared with the result when all three channels are
grounded. The difference is the channel-to-channel crosstalk,
stated in LSB.
Aperture Delay
The time delay that occurs from when a sampling edge is
applied to the AD9822 until the actual sample of the input
signal is held. Both CDSCLK1 and CDSCLK2 sample the input
signal during the transition from high to low; therefore, the
aperture delay is measured from each clocks falling edge to the
instant the actual internal sample is taken.
Power Supply Rejection
It specifies the maximum full-scale change that occurs from
the initial value when the supplies are varied over the
specified limits.
AD9822
Rev. B | Page 9 of 20
PIXEL N (R, G, B) PIXEL (N + 1)
t
AD
t
C2
t
C2ADF
t
ADC2
t
C2ADR
t
ADCLK
t
ADCLK
t
OD
ANALOG
INPUTS
CDSCLK2
ADCCLK
OUTPUT
DATA
D<7:0>
R (N– 2) G (N– 2) G (N– 2) B (N– 2) B (N– 2) R (N– 1) R (N 1) G (N– 1) G (N 1) B (N– 1) B (N– 1) R (N) R (N) G (N) G (N)
HIGH
BYTE
LOW
BYTE
HIGH
BYTE
LOW
BYTE
HIGH
BYTE
LOW
BYTE
HIGH
BYTE
LOW
BYTE
HIGH
BYTE
LOW
BYTE
HIGH
BYTE
LOW
BYTE
HIGH
BYTE
LOW
BYTE
t
ADC1
t
AD
t
C1
CDSCLK1
PIXEL
(N + 2)
00623-004
t
C2C1
t
C1C2
t
PRA
Figure 3. 3-Channel CDS Mode Timing
t
AD
PIXEL N
t
AD
ANALOG
INPUTS
t
OD
CDSCLK2
ADCCLK
OUTPUT
DATA
D<7:0>
t
C2
PIXEL
(N – 4)
PIXEL
(N – 4)
PIXEL
(N – 3)
PIXEL
(N – 3)
PIXEL
(N – 2)
PIXEL
(N – 2)
t
C1C2
t
C1
CDSCLK1
t
ADC1
HIGH BYTE LOW BYTE LOW BYTEHIGH BYTE LOW BYTEHIGH BYTE
PIXEL (N + 1) PIXEL (N + 2)
t
C2ADR
00623-005
t
C2C1
t
PRB
t
C2ADF
t
ADCLK
t
ADCLK
Figure 4. 1-Channel CDS Mode Timing

AD9822JRSZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog Front End - AFE 14-Bit CCD/CIS Signal Processor
Lifecycle:
New from this manufacturer.
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