AD9822
Rev. B | Page 16 of 20
ANALOG INPUTS—SHA MODE
Figure 12 shows the analog input configuration for the SHA
mode of operation. Figure 13 shows the internal timing for the
sampling switches. The input signal is sampled when CDSCLK2
transitions from high to low, opening S1. The voltage on the
OFFSET pin is also sampled on the falling edge of CDSCLK2,
when S2 opens. S3 is then closed, generating a differential
output voltage representing the difference between the sampled
input voltage and the OFFSET voltage. The input clamp is
disabled during SHA mode operation.
AD9822
S1
2pF
S3
CML
VINR
INPUT SIGNAL
S2
2pF
CML
OFFSET
RED
VING
GREEN
VINB
BLUE
OPTIONAL DC OFFSET
(OR CONNECT TO GND)
00623-013
Figure 12. SHA Mode Input Configuration (All Three Channels are Identical)
CDSCLK2
Q3
(INTERNAL)
S1, S2 CLOSED S1, S2 CLOSED
S3 CLOSED S3 CLOSED
S3 OPEN
S1, S2 OPEN
00623-014
Figure 13. SHA Mode Internal Switch Timing
Figure 14 shows how the OFFSET pin may be used in a CIS
application for coarse offset adjustment. Many CIS signals have
dc offsets ranging from several hundred millivolts to more than
1 V. By connecting the appropriate dc voltage to the OFFSET
pin, the CIS signal is restored to 0. After the large dc offset is
removed, the signal can be scaled using the PGA to maximize
the ADC’s dynamic range.
AD9822
OFFSET
RED-OFFSET
GREEN-OFFSET
BLUE-OFFSET
VINR
VING
VINB
RED
GREEN
BLUE
0.1µF
AVDD
VREF FROM
CIS MODULE
DC OFFSET
R1
R2
SHA
00623-015
SHA
SHA
Figure 14. SHA Mode Used with External DC Offset
PROGRAMMABLE GAIN AMPLIFIERS (PGA)
The AD9822 uses one PGA for each channel. Each PGA has a
gain range from 1× (0 dB) to 5.8× (15.5 dB), adjustable in
64 steps. Figure 15 shows the PGA gain as a function of the
PGA register code. Although the gain curve is approximately
linear-in-dB, the gain in V/V varies nonlinearly with register
code, following the equation
+
=
63
63
4.71
5.7
G
Gain
where G is the decimal value of the gain register contents and
varies from 0 to 63.
00623-016
GAIN (V/V)
1.0
5.7
4.0
5.0
2.0
3.0
PGA REGISTER VALUE (Decimal)
630 4 8 12162024283236404448525660
GAIN (dB)
15
12
9
6
3
0
Figure 15. PGA Gain Transfer Function
AD9822
Rev. B | Page 17 of 20
APPLICATIONS
CIRCUIT AND LAYOUT RECOMMENDATIONS
Figure 16 shows the recommended circuit configuration for
3-channel CDS mode operation. The recommended input
coupling capacitor value is 0.1 µF (see the Circuit Operation
section). A single ground plane is recommended for the
AD9822. A separate power supply may be used for DRVDD,
the digital driver supply, but this supply pin should still be
decoupled to the same ground plane as the rest of the AD9822.
The loading of the digital outputs should be minimized, either
by using short traces to the digital ASIC or by using external
digital buffers. To minimize the effect of digital transients
during major output code transitions, the falling edge of
CDSCLK2 should occur coincident with or before the rising
edge of ADCCLK (see Figure 3 through Figure 6 for timing).
All 0.1 µF decoupling capacitors should be located as close as
possible to the AD9822 pins. When operating in single-channel
mode, the unused analog inputs should be grounded.
Figure 17 shows the recommended circuit configuration for
3-channel SHA mode. All of the above considerations also apply
for this configuration, except that the analog input signals are
directly connected to the AD9822 without the use of coupling
capacitors. The analog input signals must already be dc-biased
between 0 V and 2 V (see the Circuit Operation section).
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
AD9822
CDSCLK1 AVDD
CDSCLK2
ADCCLK
OEB
DRVDD
DRVSS
D7 (MSB)
D6
D5
D4
D3
D2
D1
D0 (LSB)
AVSS
VINR
OFFSET
VING
CML
VINB
CAPT
CAPB
AVSS
AVDD
SLOAD
SCLK
SDATA
3
CLOCK INPUTS
8
DATA OUTPUT
S
0.1µF
3
SERIAL INTERFACE
0.1µF
5V/3V
5V
0.1µF
0.1
µ
F
0.1µF
0.1µF
RED INPUT
GREEN INPUT
BLUE INPUT
0.1µF
0.1µF 1.0µF
0.1µF
0.1µF
+
10µF
5V
0.1µF
00623-017
Figure 16. Recommended Circuit Configuration, 3-Channel CDS Mode
00623-018
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
AD9822
CDSCLK1 AVDD
CDSCLK2
ADCCLK
OEB
DRVDD
DRVSS
D7 (MSB)
D6
D5
D4
D3
D2
D1
D0 (LSB)
AVSS
VINR
OFFSET
VING
CML
VINB
CAPT
CAPB
AVSS
AVDD
SLOAD
SCLK
SDATA
3
CLOCK INPUTS
8
DATA OUTPUT
S
0.1µF
3
SERIAL INTERFACE
0.1µF
5V/3V
5V
0.1µF
RED INPUT
GREEN INPUT
BLUE INPUT
0.1µF
0.1µF
0.1µF
+
10µF
5V
0.1µF
Figure 17. Recommended Circuit Configuration, 3-Channel SHA Mode (Analog Inputs Sampled with Respect to Ground)
AD9822
Rev. B | Page 18 of 20
OUTLINE DIMENSIONS
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
COMPLIANT TO JEDEC STANDARDS MS-013AE
0.33 (0.0130)
0.20 (0.0079)
0.75 (0.0295)
0.25 (0.0098)
× 45°
1.27 (0.0500)
0.40 (0.0157)
SEATING
PLANE
0.30 (0.0118)
0.10 (0.0039)
0.51 (0.0201)
0.31 (0.0122)
2.65 (0.1043)
2.35 (0.0925)
1.27 (0.0500)
BSC
28 15
14
1
18.10 (0.7126)
17.70 (0.6969)
10.65 (0.4193)
10.00 (0.3937)
7.60 (0.2992)
7.40 (0.2913)
COPLANARITY
0.10
Figure 18. 28-Lead Standard Small Outline Package [SOIC]
Wide Body (R-28)
Dimensions shown in millimeters and (inches)
0.25
0.09
0.95
0.75
0.55
0.05 MIN
1.85
1.75
1.65
2.00 MAX
0.38
0.22
SEATING
PLANE
0.65
BSC
COPLANARITY
0.10
28 15
14
1
10.50
10.20
9.90
5.60
5.30
5.00
8.20
7.80
7.40
PIN 1
COMPLIANT TO JEDEC STANDARDS MO-150AH
Figure 19. 28-Lead Shrink Small Outline Package [SSOP]
(RS-28)
Dimensions shown in millimeters
ORDERING GUIDE
Model Temperature Range Package Description Package Options
AD9822JR 0°C to 70°C 28-Lead SOIC R-28
AD9822JRRL 0°C to 70°C 28-Lead SOIC R-28
AD9822JRS 0°C to 70°C 28-Lead SSOP RS-28
AD9822JRSRL 0°C to 70°C 28-Lead SSOP RS-28
AD9822JRSZ
1
0°C to 70°C 28-Lead SSOP RS-28
AD9822JRSZRL
1
0°C to 70°C 28-Lead SSOP RS-28
1
Z = Pb-free part.

AD9822JRSZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog Front End - AFE 14-Bit CCD/CIS Signal Processor
Lifecycle:
New from this manufacturer.
Delivery:
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